EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Digital Design with VHDL Lecture 13

3. Hierarchy in Large Designs A simple microprocessor design

4. Hierarchical Design

5. Hierarchical Design (Cont’d)

6. Block diagram of a processor

7. Top-level Structural code entity processor is port (clk: in std_logic; reset: in std_logic; output: out std_logic_vector (15 downto 0)); end processor; architecture structural of processor is component datapath is port (…………… end component; //declare all the other components // //define a bunch of signals interconnecting the components// begin u1: datapath port map (.......) end structure;

8. Design of the ALU • Pair of n-bit operands (A [n:0], B [n:0]) • Logic and Arithmetic operations, controlled by opcode

9. Operations of the ALU

10. Example Code of the ALU architecture behav of ALU is signal alu_temp: std_logic_vector (3 downto 0); begin process (A, B, opcode) begin case opcode is when “00” => alu_temp <= A + B; when “01” => alu_temp <= A – B; ………………………………… end process; alu_out <= alu_temp;

11. Register File

12. Creating a Register Replication of flip-flop cell cell_array : forbit_indexin 0 to width-1 generate signaldata_unbuffered : std_logic; begin cell_storage : componentD_flipflop port map (clk => clock, d=>data_in(bit_index), q => data_unbuffered); cell_buffer : componenttristate_buffer port map (a=>data_unbuffered, en=>out_enable, y=>data_out (bit_index)); end generatecell_array

13. Bit-vector Arithmetic Package Creation of a arithmetic package package bv_arithmetic is function bv_to_natural (bv : in bit_vector) return natural; function natural_to_bv (nat : in natural; length: in natural) return bit_vector; function bv_to_integer (bv : in bit_vector) return integer; function “+” (bv1, bv2 : in bit_vector) return bit_vector; ……………………..

14. ALU using the Arithmetic Package Bit-vector arithmetic package is analyzed and placed in a design library called bv_utilities library ieee; use ieee.std_logic_1164.all; package alu_types is subtype alu_func is std_ulogic_vector (3 downto 0); constant alu_add : alu_func := “0000”; constant alu_sub : alu_func := “0001”; ……………………………….. end package alu_types;

15. ALU Entity library ieee; use ieee.std_logic_1164.all; use work.alu_types.all; entity alu is port (s1, s2 : in std_ulogic_vector; result : out std_ulogic_vector; func : in alu_func; zero, negative, overflow : out std_ulogic); end entity alu;

16. ALU Architecture librarybv_utilities; architecture behavior of aluis begin alu_op: process (s1, s2, func) use bv_utilities.bv_arithmatic.all; begin ……………………………… casefuncis whenalu_add => bv_add (………………………..) ………………….

17. Memory block entity memory is port (clk: in std_logic; rst: in std_logic; mre: in std_logic; mwe: in std_logic; address: in std_logic_vector (7 downto 0); data_in: in std_logic_vector (15 downto 0); data_out: out std_logic_vector (15 downto 0)); end memory; architecture behav of memory is type ram_type is array (0 to 255) of std_logic_vector (15 downto 0); signal tmp_ram: ram_type; …………………………………………………………………………………………………………………

18. Memory write and read begin write: process (clk, rst, mwe, mre, address, data_in) begin if (rst = 1) then ………………… else if (clock'event and clock = '1') then if (mwe ='1' and mre = '0') then tmp_ram(conv_integer(address)) <= data_in; end if; ………………………………… read: process (clk, rst, mwe, mre, address) begin if rst='1' then data_out <= ZERO; else if (clock'event and clock = '1') then if (Mre ='1' and Mwe ='0') then data_out <= tmp_ram(conv_integer(address)); end if; ………………………………………………………

19. Memory Interface Unit

20. Program Counter architecture behv of PC is signal tmp_PC: std_logic_vector(15 downto 0); begin process (PCclr, PCinc, PCld, PCin) begin if PCclr='1' then tmp_PC <= ZERO; elsif (PCld'event and PCld = '1') then --elsif PCld = '1' then tmp_PC <= PCin; elsif (PCinc'event and PCinc = '1') then --elsif PCinc = '1' then tmp_PC <= tmp_pc+ 1; end if; end process; PCout <= tmp_PC; end behv;