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Simulation results. A. 10. 20. 30. 40. 50. 60. time [ns]. C5. 10 ns. 20 ns. PROVE-C5- cir:. ENTITY cir IS PORT (a: IN BIT; c5: OUT BIT); END cir; ARCHITECTURE bhv OF cir IS BEGIN p5: process begin c5 <= not a;
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Simulation results A 10 20 30 40 50 60 time [ns] C5 10 ns 20 ns
PROVE-C5-cir: ENTITY cir IS PORT (a: IN BIT; c5: OUT BIT); END cir; ARCHITECTURE bhv OF cir IS BEGIN p5: process begin c5 <= not a; wait until a='1' for 10 ns; end process; end bhv;
ENTITY stm IS PORT (a:OUT BIT;c5:IN BIT); END stm; ARCHITECTURE dtf OF stm IS BEGIN a<= '0' AFTER 0 ns, '1' AFTER 20 ns, '0' AFTER 28 ns, '1' AFTER 45 ns, '0' AFTER 58 ns; END dtf; 2.) stm:
ENTITY bnc IS END bnc; use std.textio.all; ARCHITECTURE str OF bnc IS COMPONENT cir PORT (a: IN BIT;c5:OUT BIT); END COMPONENT; COMPONENT stm PORT (a:OUT BIT;c5:IN BIT); END COMPONENT; SIGNAL wa,wc5: BIT; for all: cir use entity work.cir (bhv); for all: stm use entity work.stm (dtf); signal s,z:Boolean:=False; 3.) bnc:
BEGIN circuit: cir PORT MAP(wa,wc5); generator: stm PORT MAP(wa,wc5); -- Header of the results header: process variable dline1: line; variable dline2: line; constant L1: string:="This is the operation of the D-FlipFlop"; constant L2: string:=" TIME a c5 "; begin write (dline1, L1, right, 1); writeline (output, dline1);
write (dline2, L2, right, 1); writeline (output, dline2); s<=True; wait; end process; -- Monitoring the result and printing them out monitor: process (wa,wc5) variable dline: line; begin if s=True and z=True then write (dline, NOW, right, 8); write (dline, wa, right, 7);
write (dline, wc5, right, 7); writeline (output, dline); end if; end process; -- This is a line, only Underline: process variable dline: line; constant L: string:="==============================="; begin wait on s; write (dline, L, right, 1);
writeline (output, dline); z<=True; end process; END str;
