A High Performance SoC: Pkunity TM

1. A High Performance SoC: PkunityTM Chen Jie Peking University Microprocessor R&D Center

2. Contents • PkUnity SoC Introduction • PkUnity SoC Low Power Design

3. Introduction

4. PKUnity-3 Architecture

5. UniCore fix-point processor • UniCore Frequency: 600MHz • 32-bit harvard-architecture RISC CPU • UniCore32 instruction set compatible • Add conditional mov & BLX instructions • 8-stage instruction pipeline • Dynamic prediction policy: G-share • Pipelined I&D Cache • Two-level TLB

6. Performance Evaluation • Unicore-II CPI increase 10％-15% • G-share prediction, pipelined cache, two-level TLB reduce the increasing of CPI caused by deep pipeline • UniCore-II MIPS increase 70%- 80 % • Performance improvement come from improvement of micro-architecture and technology

7. SoC Design Platform • To build : • a chip-based infrastructure • a integrated develop environment • a design and verification flow • In PkUnity-3: • CPU configurable • BUS configurable • Interrupt system configurable • DMA configurable • Frequency configurable • Power management

8. Verification Coverage-oriented VERA verification flow SystemC-based HW/SW Co-verification methodology FPGA prototype

9. Contents • PkUnity SoC Introduction • PkUnity SoC Low Power Design • Power research status • PkUnity low power design and power estimation • Future work

10. Power : New Challenge • Power is a dramatic issue for SoCs with billions of transistors • Power has to be reduced for portable devices that require a dramatic increase of computation power • Deep submicron technologies (90 and 65 nm) will present a dramatic increase of leakage power • Power still too high for most SoCs • SoC Architectures, HW/SW, multiprocessor, multiple memories, are not well supported by CAD tools • Reconfigurability and Flexibility compromises low-power • Leakage and very low Vdd are dramatic problems

11. LP Research Condition low power design technology and research topics Technology Feature size shrink, low dielectric constant material, SOI technology Circuit Design low power standard cell library Gate Design low power logic chain: gated clock, gated Vdd RTL reduce switching activity: gated clock, state machine & glitch optimization Micro-arch • Parallel, Pipeline, Pre-computing Instruction • Good task partition between HW/SW, design low power instruction set Compiler • Saving power while improve performance, Memory organization OS • Dynamic voltage scaling, I/O devices, Power and energy analysis of OS Application • Task partition, Algorithm optimization

12. Power Estimation Research Analysis Precision Analysis Speed System Algorithm Register Transfer Logic Circuit Power Estimation Hierarchy High level architectural model SimplePower simulation vs. analysis Wattch CACTI simulation with timing info extract circuit parameters adding technology info gate level simulation PrimePower PowerCompiler analysis with extractive parameter HSPICE

13. Power of Pkunity • Embedded Processor: High Performance vs. Low Power • Three methods to reduce chip power: • Close unused module • Frequency scaling • Close Pll • Pkunity-3 object: • CPU <800mW@1.8V/600MHz • SoC <2000mW@1.8V/600MHz

14. Power Estimation

15. Power optimization • Close unused module through gated clock • Reduce chip power through scaling among multiple run mode • Run • Idle • Sleep • Change chip frequency through dynamic PLL configuration • Input vector control in Execution components

16. Work Flow Low power design and estimation flow

17. Future Work • Low Power Design • Memory architecture (cache, TLB, register file) • Clock system ( Syn vs. Asyn ) • Bus system • Instruction set selection • Voltage and frequency scaling • Compiler optimization • Task movement • Power Estimation • To pre-analyze arch & micro-arch design through fast and accurate Architectural level power simulator • To build a full-chip power simulator • Power simulator parameter reconfigurable • To build accurate leakage power estimation model • Specific component power model

18. Thank you