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Seminar for the Class of Digital Systems Electronics. R. Antonicelli ST Belgium, Network Division. The VHDL simulation environment. Polytechnic of Bari May 5 – 7, 2004. What is simulation good to?.
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Seminar for the Class of Digital Systems Electronics R. Antonicelli ST Belgium, Network Division The VHDL simulation environment Polytechnic of Bari May 5 – 7, 2004
What is simulation good to? • When we write down a VHDL code, we must ensure a good matching between the digital circuit and our model • Thus, we need to check every signal and monitor the source code step by step • With a simulator tool we can easily reach these goals
What simulators are often used? • Modelsim by Mentor Graphics * * * * * • Leapfrog by Cadence * * * • Saber by Cadence * • VSS by Synopsys *
Modelsim EE/SE We discuss now about Modelsim simulator tool
Modelsim EE: Graphic interface Main window
Modelsim EE: Graphic interface Wave window
Modelsim EE: Graphic interface Wave window
Modelsim EE: Graphic interface Structure window
Modelsim EE: Graphic interface Signals window
Modelsim EE: Graphic interface Signals window
Modelsim EE: Graphic interface Variables window
Modelsim EE: Graphic interface List window
Modelsim EE: Graphic interface Source window
Modelsim EE: Lessons Create a new library
Modelsim EE: Lessons Compile a model
Modelsim EE: Lessons Load a design
Modelsim EE: Lessons Running a design
Modelsim EE: Lessons Running a design
Modelsim EE: Lessons Running a design
Modelsim EE: Lessons Managing a design