Configuring of Xilinx Virtex-II

Configuring of Xilinx Virtex-II Kjetil Ullaland, Ketil Røed, Bjørn Pommeresche, Johan Alme TPC Electronics meeting. CERN 13-14. Jan 2005

Overview • Xilinx Virtex-II configuration facts • Work so far • Results • Status

Configuring Xilinx Virtex-II • 5 built-in modes • JTAG • Master/Slave Serial • Master/Slave SelectMap • JTAG and Slave SelectMap is chosen for RCU. • 3 mode pins (M2, M1, M0) are used for setting the mode.

Configuring - details • A Xilinx Virtex is divided into Columns, which again is divided into frames. • The XC2VP4 has: • One center column (8 frames/column) • 752 CLB Colums (48 frames/column) • 4 BRAM Columns (27 frames/column) • DCM is included here • 2 IOB Columns (54 frames/column • The Column number from the start is called Major Number, and the frame number in the columns is called Minor number.

Configuring - details • Counting of the major number is 0 in the center, the even numbers to the left, and the odd to the right. • The Major and Minor numbers are used to locate a specific frame in the Virtex-II. • Writing these numbers to the FAR (Frame address register) in the FPGA, makes it possible to read or write from/to this frame.

JTAG • JTAG is the default mode. • JTAG always work whenever connected, no matter what mode is selected. • Benefits: • Well known interface that is easy to use and is supported by all companies. • Possibility to do a readback • No extra firmware/software required except what is delivered by Xilinx.

Slave SelectMap • Mode pins should be set to 110 (M2, M1, M0) • Note: If connected to a 3.3V network, these inputs must have a 100W serial resistor attached • External clock is used for configuring. • 8 bit wide databus • 6 control/status lines • Benefits: • Parallel data transport => fast interface. • Possibility to do readback of configuration memory.

Slave SelectMap • Waveform showing Slave SelectMap with Controlled Clocks. Data is clocked in at each rising edge of cclk. • Note: Prog_b should only be pulled low if clearing configuration memory.

Why use controlled clock • Second option is to use a free running clock and toggle chip select when data is ready from the sender. • This means danger for skew between clock and chip select signal, which may lead to the wrong data is transported. • Controlled clock ensures that no skew or glitches will occur, as the clock is toggled when data is put on the bus.

What is Scrubbing? • Scrubbing is when the FPGA has been reconfigured without first deleting existing configuration. • This is possible because there is a shadow register column for the configuration register columns. • A scrubbing cycle should always be preceded and followed by an abort-command, according to documentation.

Scrubbing • When doing a scrubbing cycle, it’s important to stop on the column before the BRAM content. • If deleting the BRAM contant, all values stored in RAM blocks are deleted. • Before this column, an abort is issued. • In the beginning of the configuration file, Frame 0 in Column 0 is written to the FAR register setting the starting point of the configuration. • If we want to do a partial reconfiguration, a different start address should be written to the FAR

Abort command Configuration abort sequence Readback abort sequence • Part of scrubbing procedure • The abort command is issued by toggling RDWR_B while cs_b is asserted. • An abort command lasts for at least four clock cycles. • A 32-bit abort status word is driven onto the databus during this time. • The abort ends when cs_b is deasserted.

Abort status word • Typical result according to documentation is: • 11011111 (no error, sync word received, no readback, no abort) • 11001111 (no error, sync word received, no readback, abort) • 10001111 (no error, no sync word, no readback, abort) • 10011111 (no error, no sync word, no readback, no abort)

Preparing a project in ISE • To be able to do readback or scrubbing, the selectMap bus I/O pins must stay in configuration mode after initial configuration. • Default setting is to go back to normal user I/Os • Binary configuration file should also be created. • Startup clock must be set to CCLK (for selectMap).

Files to use for configuring • <design>.bit • A binary configuration file with header information. The configuration stream start with 0xFFFFFFFF and a synch word. • If the bit file is used a search algorithm for the start of configuration stream must be added in software/firmware • <design>.bin • Same as .bit-file, but without header information • <design>.rbb • Used for readback verification. • Readback verification is a process of making a bit per bit comparison of the readback data frames to the bitmap in the <design>.rbb readback file. • <design>.msk • Used for readback verification. • Masks out irrelevant data, as not all readback data should be used for verification. • All files have approximately the same size, 368KB for the Xilinx Virtex-II XC2VP4

More information http://www.xilinx.com • Ug012.pdf • Virtex-II Pro and Virtex-II Pro FPGA User Guide • Ds083.pdf • Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet • Xapp216.pdf • Correcting Single-Event Upsets Through Virtex Partial Configuration • Xapp138.pdf • Virtex FPGA Series Configuration and Readback

Picture of setup

The test design - configuring • Changed the DCS messagebuffer-design so that Linux (ARM processor) have complete control of the RCU bus lines (data, address & ctrl) • Wrote a device driver in C that configures the design using controlled clock scheme. (Virtexdriver.c) • Made a simple design in the Altera CPLD that maps the selectMap bus to the RCU bus. • This means we have a ”tunnel” going from linux directly to the SelectMap bus.

Sketch of test design

Configuring • This made us able to use the cat-command in linux as: • cat virtexdesign.bin > /dev/virtex • The device driver then controls and responds to the control signals on the selectMap bus. • Wrote error and info messages to kernel log.

Testdesigns for Virtex-II • Two very simple test-designs were made. • Led 01 and Led 02 were physically in the same column in the Virtex FPGA.

Configuring with erasing configuration memory • Controlled from software • One of the two designs sent to the device driver using the cat command. • Without optimization the configuration time is approx. 600ms. • Time consuming: • Initialising Deivce driver • Writing to Kernel log • Buffering input file

Configuring with erasing configuration memory Beginning of config cycle Complete configuration CCLK CS_B Configuration time approx 625ms

Scrubbing • Scrubbing is tested by altering between the two different led designs, and slightly changing the virtex_driver.c code • Cat design01.bin >/dev/virtex • Cat design02.bin >/dev/virtex • Cat design01.bin >/dev/virtex • When doing this we could see leds switching in the middle of the configuration-cycle. • Because led1 and led2 are in the same physical row in the virtex, they switch at the same time. • At led3, which is driven by the same clock in both designs, there was no visible delay in the pulse. Led1 Led3 Led2

Scrubbing Led1 Led2 Led1 Led3 Led2

Results - Configuration • Clearing Configuration Memory and configuring successful • Scrubbing successful. • When doing a hard scrub cycle (deleting BRAM content), the abort word is not needed, as we are writing the complete config file. • When not deleting BRAM memory, the DCM cannot be refreshed as this in the same column as the BRAM. • Read back status word issued when doing an Abort sequence. • Depending on when the abort was issued, different words are issued. • Fits with documentation.

Results – Flash memory • Writing to Flash memory has been tested on DCS board. • Used XJTAG to write to the Flash. • XJTAG makes it possible to clock data to the correct pins on the FPGA and then shift it over to the Flash memory as an ordinary bus transaction. • We can use the JTAG chain to program the Flash by manually control the IO pins on the CPLD.

Ongoing work • Readback and verification of configuration memory. • A prototype is being designed in C, and then implemented in Firmware. • Making the firmware for the CPLD on the RCU according to presented specification.

Configuring of Xilinx Virtex-II