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T1 Electronic status

In this document, updates on the development and production progress of various electronics cards, VFAT hybrids, and components involved in the detector system at CERN are detailed. Key areas such as card layouts, production schedules, passive components, testing phases, and cabling specifications are discussed. The document also covers the procurement status of custom components, bonding processes, trigger system improvements, and future production timelines. It provides insights into the challenges faced in component association, bonding agreements, and merging trigger bits for optimal system performance. The text outlines the requirements for T1 Trigger Mezzanine boards, integration with VFAT chips, and the need for testing procedures to ensure the functionality of the detector system.

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T1 Electronic status

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  1. Electronics Cards involved: Anode Front End Card Cathode Front End Card Read-Out Control card VFAT hybrids T1 Trigger Mezzanine Other development: 16chs preamplifier. Cabling and Power Supplies: T1 Trigger Architecture Optic cabling High Voltage Low Voltage Patch panels T1 Electronic status CERN Electronics Meeting 22 Nov. 2007

  2. Electronics Cards

  3. VFAT hybrid input ground isolation new feature. 5 pieces of 1P and 5G already produced. Waiting for the components loading. Mass production launched. PCBs ready within Dec. 2007. Decision on passive components networks within Dec. 07 Components mounting within ½ Feb.08 End tests, validation and CSCs soldering March 08 AFEC

  4. First PCB almost tested. Results under evaluation New layout in progress. Ten PBCs ready 51st w/07 PCBs mounted within 2nd-3rd w/08 Decision on passive components networks within Dec. 07 Mass production ready within ½ Feb.08 End tests and validation March 08. CFEC (1)

  5. Upgrade to high resolution. New layout Jan. 08 Few prototypes ready March 08. End tests and validation April 08. Mass production ready June 08. CFEC (2)

  6. Some delays due to CERN custom components procurement. Needed to avoid wrong components packages association. Several features implemented: DOHM and CCUM emulation. DOHM I2C lines handling (follow the CCUM-SCR redundancy scheme). Trigger VFAT Mezzanine GOHs mezzanines input pattern generator. Several Data GOH DAV sources available. Several Trigger GOHs DAV sources (BC0, Static, Timed by CCUM) Foreseen a SPY Mezzanine based on T1 Digital Mezzanine. The layout is in progress. 5 PCB ready ½ Dec.07 3 Circuits mounted and tested ½ Jan.08 PCBs mass production ½ Feb. 08 Full ROCs ready within March 08. ROC (1)

  7. ROC (2)

  8. ROC (3) I/O CCUM Has been tested ??? BC0b TR_GOH_DAV TRIGGER DAV MUX IDLEb/ON I/O CCUM I/O CCUM A CSC1 MUX DATA DAV K DATA_GOH_DAV K MUX A CSC2 MUX K

  9. Hybrids production (PCBs and components mounting) at CERN. High density input connectors available from T1. Bonding may be made in Genoa. Needs agreement with the people in Genoa lab. Needs to know all the rules and material used by the CERN bonding lab. Needs some VFAT dummy chips in order to test all the procedures. Could be useful a training period at CERN of our bonding technician. Validation of the first hybrids in accord with the CERN people (W.S.- P.A.). The installation of 1 arm (30 CSCs) in March 08 involve 140 VFAT hybrids. This number is equivalent to the full T1 anode VFATS hybrids production including spares. In this installation 60 will be dedicates for the anodes and 80 for the cathodes (CFEC VFAT only based). VFAT hybrids schedule is CERN production dependent… VFAT hybrids

  10. T1 detector have 15 trigger fibers per each ¼ while each OptoRx mezzanine accept up to 12 fibers. In order to merge and manipulate with a dedicate algorithm all the trigger bits (30 fibers in total), we will need the custom TTM mezzanine to add to the Trigger TOT-FED. The trigger system is not completely fixed, need some more iterations within the trigger group. TTM not needed at the beginning (March 08). Expected to be available in June 08. T1 Trigger Mezzanine

  11. This small boards use the same FE preamplifier device integrated inside the VFAT chip (see Jan Kaplon). Needed for final studies on T1 CSC detector. Layout in progress. Some PCBs ready and mounted 2nd w/Dec.07 End tests and decision on the AFEC and CFEC passives networks components within Dec. 07 16 channels preamplifier (1)

  12. 16 channels preamplifier (2)

  13. Cabling and Power Supplies

  14. OLD Section

  15. Platform to 6th T1 Frame cable tray NEW Section Who is responsible for this cables ?? (Putting in work and purchase)

  16. 12 12 3 3 3 3 12 12 T1 TRG_TOTFED T1 TRG_TOTFED T1 Trigger Architecture Trigger Bits 2 x 480 = 960 VFAT VFAT (16bits) 8bits 8bits (16bits) ~6k wires 8 8 ~6k wires CAVERN x2 x2 1 1 CSC 2 2 CSC x2 x2 30 30 x15 x15 ROC ROC T1 ARM T1 ARM GLOBAL TRG_TOTFED TTM TTM Y X X (Needs TRG algo.) LV1 COUNTING ROOM

  17. T1 Optic Architecture (OLD version)

  18. Placed order at CERN for 5 WIENER fully equipped MARATON low voltages system. Two simple VME crates are also purchased for the MARATON remote control cards. Delivery expected within March 2008. Almost placed an order to CAEN for 6 HV modules A1550P, and one mainframe SY1527. Delivery expected March/April 2008. Low Voltage and High Voltage components.

  19. Hosted on the platform: Low voltage  it could simplify the connections with the WIENER. (not needed at the beginning) High Voltage  to be done, (not needed at the beginning) but ok for March 08. Connector procurement done. Hosted on the 6th T1 Frame: Low voltage  prototype almost ready, ok March 08. High Voltage  all produced, one prototype almost ready, ok March 08. Optic fiber  to be done, need a fiber cable fan-out and MPO connector for the dimensioning of the box (see W.S.). Patch panels

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