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Topological Array Trigger System for AGIS. Frank Krennrich (For PAT) J. Anderson, K. Byrum, J. Dawson, G. Drake, W. Haberichter, A. Krepps, M. Schroedter, A. Smith, A. IMran J. Buckley, H. Krawzcynski (WashU). Outline. Motivations Constraints Technical Approach Design
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Topological Array Trigger System for AGIS Frank Krennrich (For PAT) J. Anderson, K. Byrum, J. Dawson, G. Drake, W. Haberichter, A. Krepps, M. Schroedter, A. Smith, A. IMran J. Buckley, H. Krawzcynski (WashU)
Outline • Motivations • Constraints • Technical Approach • Design • Status & Plans
Motivations • Lowest Possible ET • Reduce Background • Limit Deadtime for DACQ • Real Time Analysis of Events • Flexible Array Operation • Other applicatiobs of GHz Trigger Systems
Rates (Night Sky) Mirror ~ 100 m2 Pixels ~ 0.15 deg. ttel ~ 10 ns tarray ~ 100 ns N.S.B. ~ 2 x 1012 m-2 sr-1 s-11
Rates (Night Sky) Mirror ~ 100 m2 Pixels ~ 0.15 deg. ttel ~ 4 ns tarray ~ 100 ns N.S.B. ~ 2 x 1012 m-2 sr-1 s-11
Rates (Night Sky) Mirror ~ 100 m2 Pixels ~ 0.15 deg. ttel ~ 7 ns tarray ~ 100 ns N.S.B. ~ 2 x 1012 m-2 sr-1 s-11
Rates (Night Sky) Mirror ~ 100 m2 Pixels ~ 0.15 deg. ttel ~ 2 ns tarray ~ 100 ns N.S.B. ~ 2 x 1012 m-2 sr-1 s-11
Further ET Reduction Focal Plane 13.3 km ( ~0.2o) • camera trigger: • - low thres. for “donut” • higher thres. For FOV • 15 - 20% threshold • reduction • (5 - 10 deg. FOV) 8 km ( ~0.5o) Aharonian et al., Astropart.Phys. 15 (2001) 335-356
Background Rejection -ray proton • 2nd moment analysis (soft cuts) reduces C.R.s by order of magnitude • Minimal Stereoscopic imaging with ~ 5 - 10 telescopes • Reconstuct shower from many poorly defined images (1st moment) taken from different viewpoints • Most effective for large array that records mostly contained events • C.R. Rejection at Trigger level eases dead time considerations
Background Rejection -ray proton • Calculate 1st & 2nd moments of images in each camera • Use stereo view from multiple telescopes to project image back into the sky • Identify g-ray images by tight correlation of projection • Do this in real-time: • ~10 MHz pixel rate à 5 GHz Camera rate (@ 500 Ch) • ~10 MHz L2 Output Rate • ~10 KHz L3 Output Rate
Min. Stereo Imag. (/hadron) • example: 19 tel. subarray • 1st moment analysis • - at least 3 tel. -rays proton showers • --> Q ~ 2.5 - 3 (point source) • ---> Q ~ 1.7 - 2 (extended source) • ---> Reduce cosmic ray rate at trigger level by 1 order of magnitude Krennrich & Lamb, Exp. Astron., vol. 6, 285 (1995)
Specifications • 400 MHz Camera Processing • Calculate 1st & 2nd moments • camera rate < 10 MHz • Transfer of image info to L3 in less than few s • L3 Trigger decision in few s • L3 rate < 50 kHz • scalable design
technical Approach ……. L1.5 L1.5 L1.5 L1.5 L1.5 L1.5 L2 L2 L3 Timing based on time stamping
Trigger Algorithm Basis • - each pixel has 6 neighbors • time window • look at pixel state • HIT if at least 2 neighbors are 3-fold coincidence • If yes, then use X-Y coordinates for pixels hit • Timestamp data • Collect X-Y coordinates of all hit pixels over entire camera • Calculate:n, Σx, Σy, Σx2, Σy2, Σxy • Send results to L3 L1.5 L2 • Neighbor logic processing at 400 MHz • Has been demonstrated in Altera Stratix II
Physical Implementation • “CameraTrigger” L1.5+L2 implemented in a 21-slot 9U Crate
Physical Implementation • I/O Cards • Receive L1 signals from front-end electronics • Copy & send across high-speed backplane to L1.5 LVDS
Physical Implementation Backplane • 9U Crate • J1: VME-64 • J2 & J3: Full Custom • point-to-point routing of buffered L1 signals, • Routing is very specific • Uses MultiGIG Connectors (Gbit/sec connectors) • 2 connectors per I/O Card (1 for primary, 1 for overlap) • 5 connectors per L1.5 • Impedance matching, differential, lots of grounds J1 - VME J2 & J3 Custom
I/O Cards • MultiGIG Connectors
I/O Cards • Status: • Schematic design complete • PCB layout complete • 10 Layers • +/-5V Power, +3.3V Regulator • Parts on order Gary Drake et al.
Backplane • Physical • Controlled impedance • +/-5V Power, screw lugs • Unused secondary signals terminated on back of backplane Gary Drake
technical Approach ……. L1.5 L1.5 L1.5 L1.5 L1.5 L1.5 L2 L2 L3
The L3 System L2 L3 T2 memory T1 FPGA T4 SFP T3 serial x4 TTL signal to VERITAS L3 ~2.5 Gbit/s fiber PCI M. Schroedter
Commercial Solution • Xilinx Virtex4-60 FPGA • Linux running on 266 MHz PowerPC in FPGA • Bidirectional Fiber • GPS clock inputs (distribute timing through L3) • 4 SFP slots • Connectors • PCI, SATA, serial • ~ $6500 www.fastertechnology.com M. Schroedter
memory memory memory SATA SATA SATA FPGA FPGA FPGA SFP SFP SFP x4 x4 x4 PCI PCI PCI …the Future ~100 L2s Daisy chain Wireless 10 Gbit Ethernet 1 km2
Status & Outlook • Proof of Principle System to built & tested • Design Review June 20 2008 Revievers: R. Ong(UCLA), J. Lewis (FNAL), T. Liu (FNAL) • Production of a full camera (500 pixels) with I/O cards, L1.5, L2 • Develop L3 concept (FPGA+PC based) • Field Test camera trigger with VERITAS telescope • Field test L3 processing • Built a complete system for 4 telscopes