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R. Leveugle, M. Ben Jrad TIMA Laboratory (Grenoble INP, UJF, CNRS )

A New Methodology for Accurate Predictive Robustness Analysis of Designs Implemented in SRAM-based FPGAs. R. Leveugle, M. Ben Jrad TIMA Laboratory (Grenoble INP, UJF, CNRS ). Outline. Introduction Previous works Methodology overview Fault injection environment Error patterns database

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R. Leveugle, M. Ben Jrad TIMA Laboratory (Grenoble INP, UJF, CNRS )

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  1. A New Methodology for Accurate Predictive Robustness Analysis of Designs Implemented in SRAM-based FPGAs R. Leveugle, M. Ben Jrad TIMA Laboratory (Grenoble INP, UJF, CNRS)

  2. Outline Introduction Previous works Methodology overview Fault injection environment Error patterns database Case study Conclusion 2

  3. Introduction • SRAM-based FPGAs are good candidates to implement complex and flexible systems • Increased sensitivity of SRAM-based FPGAs to external perturbations (radiation, particles ...) and to malicious attacks • Errors occurring in a SRAM-based FPGA can affect either the configuration memory or the user flip-flops + + Changing the configuration memory of FPGAs Change of the implemented function Modification of the data handled by the application Disturbance of the application 3

  4. Previousworks • Putting the circuit into real perturbation conditions: • Particle accelerator • Laser (Canivet 2008) • Fault injection by partial reconfiguration of a circuit prototype implemented on a SRAM-based FPGA: • The control of the reconfiguration is made by a host PC connected to the FPGA board (Antoni 2003) • The FLIPPER platform emulates SEU-like faults(Alderighi 2003) • Endo-reconfiguration using SEU model (Kenterlis 2006 - Sterpone 2007) or multiple and cumulative bit errors model (Bolchini 2009) 4

  5. Previousworks • Fault injection models are not always realistic and equipments for real perturbation conditions are not always available and are costly. Our goal is to implement a system allowing us to obtain design-time accurate robustness analyses, without resorting to costly equipments. 5

  6. Methodology overview • Our environment is implemented on a Virtex II Pro using PowerPC and ICAP. The original part of the system is not in the fault injector but in the database we added to store realistic error patterns. Injections are based on previous pre-characterization of the technological target, that can be done only one time for a given device and a given perturbation source. 6

  7. Methodology overview The actual error patterns obtained during the device pre-characterization are recorded and analyzed. Absolute values of the erroneous bits for each recorded error pattern are abstracted in order to obtain error coordinates that are relative to a CLB. The analysis of the error patterns is based for Virtex II Pro on reports generated by one module of our home-made analysis software (SEFEA-ProD). 7

  8. LUT FF LUT FF Error patterns database Relative reproduction of the error pattern in other CLBs after abstraction Recorded error pattern after a given perturbation

  9. Target device (static test) Recordederrorpatterns Physicalperturbationsources Pre-charac-terization Abstract(relative)error patterns SEFEA-ProDanalysis Abstraction Reconfiguration-basedfault injections (dynamic) Design-timeevaluations Classification,robustnessindicators Selecteddesign Finalqualification 9

  10. Case study • The selected case study is based on the Leon2 microprocessor, a Sparc V8 compliant processor, running several applications. • The database used for this case study included 5435 error patterns, obtained from laser-based perturbations. • Each pattern involved between 1 and 41 erroneous configuration bits • A single pattern can involve bits in several LUTs • Exhaustive fault injection was not possible  For a given pipeline stage and a given program between 8,000 and 160,000 pattern samples were injected so that the margin of error on the classification results is 5% with 95% confidence. 10

  11. Case study - classification • The injected error patterns were classified in 4 categories, based on the system behavior after the injection. 11

  12. Case study - results Failure & Crash : SEU FF<SEU LUT<Error patterns

  13. Conclusion • A new methodology is proposed to better evaluate at design time the actual robustness of a system implemented in a SRAM-based FPGA. • Error model based on a pre-characterization of the device (pattern database): SEUs in FFs and LUTs were found to be over-optimistic for all applications in the case study. • This approach will be used in further work to evaluate the efficiency of error mitigation techniques. 13

  14. Thankyou

  15. Case study - results • SEU FF and SEU LUT are over-optimistic for all applications with respect to the pattern database used during the experiments 15

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