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Optimizing Carry-In for Binary Invert Operation Results

Implementing a carry-in strategy to optimize binary inversion results, reducing gate delays in a ripple carry architecture. Utilizes a carry lookahead adder algorithm to minimize carry propagation, improving processing efficiency. Reduces gate delays for a more efficient 32-bit processing, enhancing computational performance.

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Optimizing Carry-In for Binary Invert Operation Results

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  1. B i n v e r t O p e r a t i o n C a r r y I n a 0 1 R e s u l t b 0 2 1 L e s s 3 C a r r y O u t B i n v e r t O p e r a t i o n C a r r y I n a 0 1 R e s u l t b 0 2 1 L e s s 3 S e t O v e r f l o w d e t e Single Bit ALU O v e r f l o w c t i o n b .

  2. CarryOut = ab + aCI + bCI a b b CI a CI + CarryOut

  3. c0 a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 2 gates c1 4 gates c2 c3 6 gates Ripple Carry c4 8 gates ci+1 = ai bi + ai ci + bi ci 10 gates c5 c6 12 Gates

  4. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0

  5. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+ b1a0c0+b1b0c0

  6. c0 a0 b0 a1 b1 c c lah c2 c1 c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+b1a0c0+b1b0c0 + c2

  7. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+b1a0b0+b1a0c0+b1b0c0 One bit lookahead ci two gate delays from ci-2 for i even Reduces gate delays for 32 bits from 64 to 32

  8. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c2 =a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+b1a0c0+b1b0c0 One bit lookahead ci two gate delays from ci-2 for i even Reduces gate delays for 32 bits from 64 to 32 c3 = a2b2+(a2+b2)c2 c4 = a3b3+(a3+b3)c3 c4 = a3b3+(a3+b3) [a2b2+(a2+b2)c2] c4 =a3b3+a3a2b2+a3a2c2+a3b2c2+b3a2b2+b3a2c2+b3b2c2

  9. c0 a0 b0 a1 b1 One Bit Lookahead a2 b2 a3 b3 c c lah c c1 c lah c2 a4 b4 a5 b5 c3 c4 c lah c 6 Gates c5 c6

  10. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c3 = a2 b2 + (a2+b2)c2 = a2 b2 + (a2+b2){a1 b1+(a1+b1)[a0 b0+(a0+b0)c0]}

  11. Carry Lookahead Adder ci is CarryIn i c1 = a0 b0 + (a0+b0)c0c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c3 = a2 b2 + (a2+b2)c2 = a2 b2 + (a2+b2){a1 b1+(a1+b1)[a0 b0+(a0+b0)c0]} Note the patterns generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci if gi = 1, ci+1 = 1, if gi = 0 and pi = 1, ci+1 = ci

  12. Carry Lookahead Adder ci is CarryIn i generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0

  13. Carry Lookahead Adder ci is CarryIn i generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0

  14. Carry Lookahead Adder ci is CarryIn i generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0

  15. Carry Lookahead Adder ci is CarryIn i generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0

  16. Carry Lookahead Adder ci is CarryIn i generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 Limited by Gate Fan-in contraints

  17. Carry Lookahead Adder ci is CarryIn i ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 c5 = g4+p4c4 c6 = g5+p5g4+p5p4c4 c7 = g6+p6g5+p6p5g4+p6p5p4c4 c8 = g7+p7g6+p7p6g5+p7p6p5g4+p7p6p5p4c4 Each 4 bit stage has 2 gate delays per stage + 1 for g & p

  18. 4 bit Carry Lookahead Using Generate & Propagate c0 a0,...,a3 b0,...,b3 generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci s0,...s3 ALU 0 c4 g p a4,...,a7 b4,...,b7 s4,...,s7 ALU 1 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 s12,...,s15 ALU 3 c16

  19. 4 bit Carry Lookahead 2nd Level Lookahead c0 a0,...,a3 b0,...,b3 so,...s3 ALU 0 c4 g p a4,...,a7 b4,...,b7 s4,...,s7 ALU 1 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 c8 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  20. G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  21. G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c13=g12+p12G2+p12P2c8 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  22. G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  23. G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c15=g14+p14g13+p14p13g12+p14p13p12G2 +p14p13p12P2c8 c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  24. G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c15=g14+p14g13+p14p13g12+p14p13p12G2 +p14p13p12P2c8 c16=g15+etc c8 g p a8,...,a11 b8,...,b11 s8,...s11 ALU 2 c12 g p a12,...,a15 b12,...,b15 G P s12,...,s15 ALU 3 c16

  25. Logical Instructions shift left logical sll Shift left shamt bits and fill with 0’s sll $s1, $s2, 10 # $s1 = $s2 << 10 op rs rt rd shamt funct 0 0 18 17 10 0

  26. Logical Instructions shift left logical sll Shift left shamt bits and fill with 0’s sll $s1, $s2, 10 # $s1 = $s2 << 10 op rs rt rd shamt funct 0 0 18 17 10 0 shift right logical srl Shift right shamt bits and fill with 0’s srl $t0, $s0, 16 # $t0 = $s0 >> 16

  27. Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct 0 17 18 16 0 36

  28. Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct 0 17 18 16 0 36 logical AND immediate andi $t0, $t1, 7 # $t0 = $t1 & (000...0111)

  29. Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct 0 17 18 16 0 36 logical AND immediate andi $t0, $t1, 7 # $t0 = $t1 & (000...0111) logical OR or $s1, $t1, $s2 # $s1 = $t1 | $s2 logical OR immediate ori $t1, $s1, 8 # $t1 = $s1 | (000..01000)

  30. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier

  31. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier 0010

  32. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier 0010 0010

  33. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier 0010 0010 0000

  34. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier 0010 0010 0000 0010

  35. Multiplication - Positive numbers Example: 0010 Multiplicand x 1011 Multiplier 0010 0010 0000 0010 0010110 Product

  36. Multiplication - Positive numbers Example: 0010 Multiplicand n bits x 1011 Multiplier m bits 0010 add 0010 shift left and add 0000 shift left and do nothing 0010 shift left and add 0010110 Product n+m bits

  37. Multiplicand Shift left 00000010 Multiplier 1011 8 bit ALU Control Test Shift right Product 00000000 1. 1 implies add

  38. Multiplicand Shift left 00000010 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000010 1. 1 implies add 2. Shift

  39. Multiplicand Shift left 00000100 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000010 1. 1 implies add

  40. Multiplicand Shift left 00000100 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000110 • 1 implies add • Shift

  41. Multiplicand Shift left 00001000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000110 • 0 no op

  42. Multiplicand Shift left 00001000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000110 • 0 no op • Shift

  43. Multiplicand Shift left 00010000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00000110 • 1 implies add

  44. Multiplicand Shift left 00010000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00010110 • 1 implies add • Shift

  45. Multiplicand Shift left 00100000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00010110

  46. Note: Half of the bits always 0 Multiplicand Shift left 00100000 Multiplier 1011 8 bit ALU Shift right Control Test Product 00010110

  47. Multiplication - Positive numbers – Shift Sum Example: 0010 Multiplicand x 1011 Multiplier 0010

  48. Multiplication - Positive numbers – Shift Sum Example: 0010 Multiplicand x 1011 Multiplier 0010 0010

  49. Multiplication - Positive numbers Multiplication - Positive numbers – Shift Sum Example: 0010 Multiplicand x 1011 Multiplier 0010 0010 00110

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