1 / 37

Computer Architecture

Computer Architecture. Lecture 3: Logical circuits, computer arithmetics Piotr Bilski. Arithmetic-Logical Unit (ALU). state pointers (flags). Performs arithmetic-logical operations Calculations are performed on the binary system numbers (Boole’s algebra). CU. ALU. registers. registers.

moya
Download Presentation

Computer Architecture

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Computer Architecture Lecture 3: Logical circuits, computer arithmetics Piotr Bilski

  2. Arithmetic-Logical Unit (ALU) state pointers (flags) • Performs arithmetic-logical operations • Calculations are performed on the binary system numbers (Boole’s algebra) CU ALU registers registers

  3. Number representations • Integer numbers: • Real numbers: MSB LSB 26 27 25 24 23 22 21 20 6110 = 0 0 1 1 1 1 0 12 1,632812510 = 1, 1 0 1 0 0 0 1 02

  4. Integer numbers (fixed point representation) • Representation of the unsignednumber A: • Sign-magnitude representation: • Two’s complement (U2):

  5. Examples (sign-magnitude) 2110 = 000101012 -2110 = 100101012 010 = 000000002 010 = 100000002 • double zero representation • addition and subtraction requires analysis of signs and magnitudes

  6. Characteristics Sign-magnitude Two’s complement Range -2n-1+1 to 2n-1-1 -2n-1 to 2n-1-1 Zero representations Two One Negation Change MSB Two’s complement Increase bits number Additional bits = 0 MSB  sign Additional bits filled with a sign Overflow Sign and magnitude analysis When signs of the operands are equal and result's opposite Subtraction Additional algorithm Adding the opposite number Integer systems characteristics

  7. Arithmetic operations on integers (1) Negation: Sign-magnitude 00010101 (21) +10000000 10010101 (-21) Two’s complement 00010101 (21) 11101010 NEG(21) +00000001 11101011 (-21)

  8. Arithmetic operations on integers (2) Conversion between lengths: Sign-magnitude 00010101 (21) 8b 00000000 00010101 (21) 16b 10010101 (-21) 10000000 00010101 (-21) 16b Two’s complements 00010101 (21) 8b 00000000 00010101 (21) 16b 11101011 (-21) 8b 11111111 11101011 (-21) 16b

  9. Arithmetic operations on integers (3) Addition: Sign-magnitude 00011001 (25) +00001101 (13) 00100110 (38) 10011001 (-25) +10001101 (-13) 10100110 (-38) 10011001 (-25) x0011001 +00001101 (13) x1110010NEG(13) 10001100 (-12) 0001011 +0000001 10001100 (-12) 10001101 (-13) x0001101 +00011001 (25) x1100110NEG(25) 00001100 (12) 1110011 R 00001100 NEG(R)

  10. Arithmetic operations on integers (4) Addition: Two’s complements 00011001 (25) +00001101 (13) 00100110 (38) 11100111 (-25) +11110011 (-13) 11011010 (-38) 11100111 (-25) +00001101 (13) 11110100 (-12) 11110011 (-13) +00011001 (25) 00001100

  11. Arithmetic operations on integers (5) • Multiplication Unsigned integers: 0111 (7) 4b 0101 (5) 4b 00000111 00000000 00011100 00000000 00100011 (35) 8b !!

  12. Increasing effectiveness of the multiplication • Every partial result can be summed at once (fewer registers!) • Multiplying by zero is only bit shifting!

  13. Hardware realization of the unsigned integersmultiplication Carry (C) Accumulator (A)

  14. Example of the hardware algorithm’s work C A Q M 0 0000 0101 0111 starting values 0 0111 0101 0111 add 0 0011 1010 0111 shift right 0 0001 1101 0111 move 0 1000 1101 0111 add 0 0100 0110 0111 shift 0 0010 0011 0111 move 0 0010 0011 0111 result

  15. Multiplication in Two’s complement representation • Signed integers: 1001 (-7)  multiplier 0011 (3)  multiplicand 11111001 11110010 11101011 (-21) Different interpretation of the binary shifting Negative number must be represented in the two’s complement code

  16. Realization of the multiplication in the Two’s complement code –Booth’s algorithm A  0, Q-1  0, LOAD(M, Q) Bit counter = n START =01 =10 Q0, Q-1 A  A - M A  A + M =11 =00 NO Bit count.=0 Right shifting A, Q, Q-1 Bit counter = bit counter - 1 YES STOP

  17. Example of the Two’s complement code multiplication (7 x 3 operation) A Q Q-1 M 0000 0011 0 0111 starting values 1001 0011 0 0111 subtract 1100 1001 1 0111 shift arithmetically 1110 0100 1 0111 shift arithmetically 0101 0100 1 0111 add 0010 1010 0 0111 shift arithmetically 0001 0101 0 0111 shift arithmetically 0001 0101 0 0111 result

  18. Division of unsigned integers A  0, LOAD(M, Q) Bit counter = n Move A,Q left START A  A - M YES NO A < 0? Q0 0 A  A + M Q0 1 NO Bit count.=0 Bit counter = bit counter - 1 YES STOP

  19. Division of integers in Two’s complement representation LOAD(A, M, Q) Bit counter = n Move A,Q left START restore A NO YES signs A, M identical? A  A - M A  A + M Oper. successful? NO NO YES Q0 0 Q0 1 Bit count.=0 Bit counter = bit counter - 1 YES STOP

  20. Example of the Two’s complement representation division (–7/3 operation) A Q M 1111 10010011 starting values • 0010 0011 shift left 0010 add 1111 0010 0011 restore 1110 01000011 shift left 0001 add 1110 01000011 restore • 1000 0011 shift left 1111 add 1111 1001 0011 set Q0 = 1 1111 0010 0011 shift left 0010 add 1111 0010 0011 restore 1111 0010 0011 result

  21. Floating point representation • Used to represent very small and very large numbers • Form the following number: where: m – mantissa c – exponent b - base

  22. Examples 1.24 x 107 (1.24e7) 5.82 x 10-21 0.010110 x 2110101 0.001001 x 16101 Format of the 32-bit floating point number: mantissa exponent 23 bits 8 bits sign

  23. 0 0,125 0,0625 0,53125 0,5 0,25 0,265625 0,125 x 2 0,25 x 2 0,5 x 2 0,6328125 x 2 0,53125 x 2 0,265625 x 2 0,0625 x 2 0,125 0,5 1,0 1,265625 0,25 0,53125 1,0625 1 0 0 1 0 1 0 Representation of the floating point binary number 1,6328125 x 220 = 1.1010001 x 210100

  24. Representation of the binary floating-point number • Exponent is a displaced number at 127, so 20 = 127 + 20 = 147 (as above) 1,6328125 x 220 = 1.1010001 x 210100 10100010000000000000000 10010011 0

  25. Normalization of the floating-point number • Exponent is changed, so the first mantissa’s digit before the comma was non-zero • Because the non-zero number is 1, it does not have to be stored

  26. Range and accuracy of the floating-point numbers For the 32-bit number: • Exponent is 8-bit, so range is +-2256 • Mantissa is 23-bit, so accuracy is 2-23 = 1.2 x 10-7 We make a compromise between the accuracy and range

  27. Density of the floating point numbers positive underflow negative underflow positive overflow negative overflow zero -n 0 n 2n 4n

  28. Standard IEEE 754 • Apllied standard of storing floating point numbers • Refers to the 32- i 64-bit numbers • Exponent of length, respectively, 8 i 11 bits • Default base is 2 • Predefined formats for the indirect calculations

  29. Special values in IEEE 754 • c = 0, m = 0 – positive or negative zero • c = 11111111, m = 0 – positive or negative infinity • c = 0, m  0 - denormalized number (bit on the left from the comma is zero!) • c = 11111111, m  0 - NaN

  30. Floating point arithmetics Basic operations:

  31. Addition and subtraction • Checking for zeros • Equalization of mantissas • Adding or subtracting of mantissas • Result normalization Example: (123 x 100)+(456 x 10-2)=(123 x 100)+(4,56 x 100) = = 127,56 x 100

  32. Multiplying and dividing • Checking zeros • Adding exponents and subtracting shifted values from the sum • Checking for exponent overflow and underflow • Multiplication of the mantissas considering signs (sign-magnitude representation!) • Rounding and normalization of the multiplication result

  33. Logical structures (1) Basic gates: A B Y 0 0 0 0 1 0 1 0 0 1 1 1 A B Y Y = A AND B A B Y 0 0 0 0 1 1 1 0 1 1 1 1 A B Y Y = A OR B A Y 1 0 0 1 A Y A = NOT Y

  34. Logical structures (2) Additional gates: A B Y 0 0 1 0 1 1 1 0 1 1 1 0 A B Y Y = A NAND B A B Y 0 0 1 0 1 0 1 0 0 1 1 0 A B Y Y = A NOR B A B Y 0 0 0 0 1 1 1 0 1 1 1 0 A B Y Y = A XOR B

  35. Logical structures (3) Half-adder A B S C 0 0 0 0 0 1 1 0 1 0 - - 1 1 - - A B S C A S B C

  36. Logical structures (4) Adder A B Ci S Co 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 Ci A B S Co A S B C A S B C

  37. Logical structures (5) 4-bit adder S0 S1 S2 S3 C1 C4 C2 C3 0 A0 B0 A1 B1 A2 B2 A3 B3

More Related