VTX LVL-1 “Strawman”

1. VTX LVL-1 “Strawman” • So what is a “strawman”? • It’s something nobody believes • It’s stuffed with “highly combustible material” • It exists to be shot at • What follows is a collection of ideas • Mostly collected/stolen from others • Nothing is fully worked out • Ready, Aim, ….. VTX Level-1 Strawman - J. Lajoie

2. Boundary Conditions • Recent discussions regarding VTX and LVL1: • Limited LVL1 Bandwidth (~8kHz) • See Tony Frawley’s Heavy PWG presentation: http://www.phenix.bnl.gov/WWW/p/draft/frawley/vtx/vtx_trigger/ • Upgraded LVL1 Bandwidth (~20kHz) • See Jamie’s email, Yasuyuki’s presentation https://www.phenix.bnl.gov/phenix/WWW/p/lists/phenix-trigger-l/recent/msg02958.html https://www.phenix.bnl.gov/phenix/WWW/p/draft/akiba/04.05/05.19VTX • Both scenarios assume data recording bandwidth will grow to accommodate LVL1 accept rate • Hardware Level-2 options are not the issue • This talk won’t discuss if we need LVL1 for VTX • I’m just going to try to point out what we have available to work with. VTX Level-1 Strawman - J. Lajoie

3. Barrel Options Fast OR option for “diagnostic testing and self triggering” • ALICE chip pixel layers • Fast “OR” option on a pixel chip level (Axel) (pp minbias) • Open issues • Thresholds? Noise? • Readout? • Physics? • See Alan’s presentation • No pixel-level LL1 option • Strip sensor layers • SVX4 readout • No LL1 Option (!) • PHX readout • Similar LL1 option to endcaps (see following) • What’s potentially available at LVL1 for the barrel? • Minimum bias pp trigger using pixel fast OR • Not necessarily designed for this • Won’t work unless we spec it NOW! VTX Level-1 Strawman - J. Lajoie

4. VTX Endcap Options • Endcap readout is PHX chip • Push readout technology • Require a FEM interface to match to PHENIX • Very natural place to interface to an LVL1 system • Endcap physics (pp, dAA, AA) may require a displaced vertex trigger • Very technically challenging • 4 stations per endcap • Zero suppressed, 3-bit ADC, ~1% occupancy • 2 million channels(!) • We can adopt a similar approach to that used in BTeV and/or LHCb • FPGA coprocessing required DCM Data Async Data Endcap FEM L1 accept To LL1 VTX Level-1 Strawman - J. Lajoie

5. LHCb Algorithm (Slide Stolen from G. Kunde, from work w/Ivan Kissel) 1) Tracking efficiency 97—99% 2) PV resolution 46 mm 3) Timing 4.8 ms CPU Expect a factor 7—8 in CPU power in 2007 (PASTA report) => we are already within 1 ms ! 4.8 ms  Events 17 ms FPGA co-processor  time (ms) Mean: 15 ms  Events • Cellular Automaton algorithm • FPGA co-processor at 50 MHz • 8 processing units running in parallel • => 15 ms !  time (ms) VTX Level-1 Strawman - J. Lajoie

6. Turn the Problem Around… https://www.phenix.bnl.gov/phenix/WWW/p/lists/phenix-trigger-l/recent/msg02970.html • Consider triggering in pp: • Forward upgrade buys you a muon momentum cut • K/pi decay is irreducible muon background • 4 GeV cut keeps ~50% of beauty physics, ~17% of charm (also correlates with x) • If this is unacceptable for charm we need to do something different…. • Two Options • Hard(?): trigger on ~100um displaced vertex • Easy(?): reject few cm displaced vertices from K/pi decay 2.3 GeV (min. to penetrate MuID) VTX Level-1 Strawman - J. Lajoie

7. Conclusions (?) • We need to know more about what we’re shooting at! • Maybe it’s obvious by this point in the meeting? • Barrel: Minimum Bias pp trigger? • Could be done with simple barrel pixel OR • Additional simulations/study needed • Feedback from the Spin Task Force (imminent) • Endcap Options? • Limited LVL1 Bandwidth: • Probably need to start thinking about LVL1 seriously • FPGA coprocessing solution a must • Close to Full LVL1 Bandwidth • Need a plan, allocate resources for demultiplex/DCM upgrades • May still need an LVL1 for endcaps to reduce charm background • Can we put “all our eggs in one basket”? • Keep an LVL1 option open in the endcap FEM design? VTX Level-1 Strawman - J. Lajoie