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Computer Architecture

Computer Architecture. Verilog HDL. The Verilog Language. Originally developed by Gateway Design Automation as a propriety language for logic simulation in 1984 Later put into use as a specification language for logic synthesis

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Computer Architecture

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  1. Computer Architecture Verilog HDL

  2. The Verilog Language • Originally developed by Gateway Design Automation as a propriety language for logic simulation in 1984 • Later put into use as a specification language for logic synthesis • Now, one of the two most commonly used languages in digital hardware design (VHDL is the other) • Virtually every chip (FPGA, ASIC, etc.) is designed in part using one of these two languages • Supports both structural and behavioral modeling styles

  3. Behavioral Modeling with Continuous Assignments input/output specification

  4. Bitwise Operators comments

  5. Reduction and Other Operators

  6. Internal Signals internal signal

  7. Precedence

  8. Constants

  9. Hierarchy

  10. Tristates high impedance

  11. Bit Swizzling

  12. Behavioral Modeling with Always Blocks sensitivity list

  13. Behavioral Modeling with Always Blocks

  14. Latches & Counters

  15. Combinational Logic dependent on all inputs

  16. Combinational Logic

  17. Combinational Logic

  18. Memories

  19. Nonblocking & Blocking Assignments

  20. Nonblocking & Blocking Assignments incorrect!

  21. Finite State Machines

  22. Parameterized Modules

  23. Pitfalls • Incorrect Stimulus List

  24. Pitfalls • Missing begin/end Block

  25. Pitfalls • Undefined Outputs

  26. Pitfalls • Incomplete Specification of Cases

  27. Pitfalls • Shorted Outputs

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