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The Testing Issues on System-in-Package Design Methodology

The Testing Issues on System-in-Package Design Methodology. Speaker ： Meng-Syue Chan Advisor ： Chun-Yao Wang 2008-07-10 Department of Computer Science National Tsing Hua University, Taiwan. Outline. Introduction Quality-Cost Evaluation Models Interconnect Testing

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The Testing Issues on System-in-Package Design Methodology

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  1. The Testing Issues on System-in-Package Design Methodology Speaker：Meng-Syue Chan Advisor：Chun-Yao Wang 2008-07-10 Department of Computer Science National TsingHua University, Taiwan

  2. Outline Introduction Quality-Cost Evaluation Models Interconnect Testing Experimental Results Conclusions

  3. Introduction With the advance of semiconductor technologies, the number of transistor in a chip is increasing exponentially This leads a large system can be realized in a single chip, this design methodology is named System-on-a-chip (SoC)

  4. What is SoC An SoC typically integrates various cores and intellectual properties (IPs), which are developed in-house or purchased from IP vendors SoC design methodology has a great integration of versatile cores, but it suffers a lower yield from the large die size

  5. What is SiP An SiP consists of several bare dies which are placed on the common substrate horizontally or vertically within the same package Designers can integrate a variety of dies which are manufactured separately with the most advanced technologies and tested

  6. The Benefits of SiP The yield of SiP design may be elevated without sacrificing time-to-market and miniaturization On the other hand, SiP also introduces a solution to protect the intellectual property of IP vendors, due to dies delivery instead of cores delivery

  7. Some Issues on SiP Manufacturing cost Low assembly yield Non-guaranteed bare dies quality Thermal management

  8. Outline Introduction Quality-Cost Evaluation Models Interconnect Testing Experimental Results Conclusions

  9. Motivation In order to guarantee the quality of the SiP design, we can use thehighest quality components and apply the testing strategies with thehighest fault coverage But in actual situation, the development and manufacturing budget must be under control

  10. Our Approach • We propose a model to find the best solution under the constraints such as the budget or quality constraints • There are two cases in our approach • Minimizes the cost of the product and keeps its quality • Enhances the quality of the product under the budget

  11. Apply SAT to the Constraint • Minimize: • aX1+bX2+cX3+dX4 • a, b, c, and d are constants • All Xi are binary numbers • Subject to : • (X1+X2)(X2+X3+X4)=1 • Other constraints • Minimize: • aX1+bX2+cX3+dX4 • a, b, c, and d are constants • All Xi are binary numbers • Subject to : • X1 + X2=1 • X2+X3+X4=1 • Other constraint

  12. Apply SAT to the Constraint • Minimize: • aX1+bX2+cX3+dX4 • a, b, c, and dare constants • All Xi are binary numbers • Subject to : • (X1+X2)(X2+X3+X4)=1 • Other constraint equations (X1+X2)(X2+X3+X4)=? (X1+X2)(X2+X3+X4)=1 Then Calculate & Record (X1+X2)(X2+X3+X4)=1 Then Calculate & Record

  13. The Definition of Defect Level • Defect Level is the percentage of components passing all testing which are still defective • For single circuit or chip • Defect Level = 1-yield(1-fc) • yield is the probability of a good die • fc is the fault coverage

  14. The Definition of Defect Level • We can rewrite the equation to • Defect Level = 1-Π{Yi(1-fcj)} • For example: Defect Level = 1-{(0.9)(1-0.8)(0.95) (1-0.99) } • This equation can be used on a multiple bare dies design, and the defect level can be a benchmark to evaluate the quality of a design

  15. The Evaluation Model with Quality Constraint • Minimize: • Cost = Σ(XiCi) + W • All Xi are binary numbers • Ci is the price of the item • W is the average payment of each product • Subject to: • Π(Xi+Xi+1+....+Xi+(n-1)+Xi+n) = 1 • W = Fine × (Defect Level) • Defect Level < The constraint

  16. An Example Assume that there are two functionalities A and B in the SiP , and the SiP has one bare die of functionality A; two bare dies of functionality B It also has several testing strategies for corresponding bare dies

  17. The Detailed Data of the Example

  18. An Example of Our Evaluation Model with Quality Constraint • Minimize: • (5X1+7X2+8X3)+(13X4+15X5)+(13X6+15X7)+(10X8+15X9)+ (10X10+20X11+50X12)+(10X13+20X14+50X15)+W • Subject to: • (X1+X2+X3)(X4+X5)(X6+X7)(X8+X9)(X10+X11+X12)(X13+X14+X15)=1 • 106×(Defect Level)<9,000 • W=(Defect Level)×10,000

  19. An Example of Our Evaluation Model with Defect Level Constraint • The best solution is (X3, X5, X7, X9, X11, X14) • Minimize: • (5X1+7X2+8X3)+(13X4+15X5)+(13X6+15X7)+(10X8+15X9)+ (10X10+20X11+50X12)+(10X13+20X14+50X15)+W =$180.20 • Subject to: • (X1+X2+X3)(X4+X5)(X6+X7)(X8+X9)(X10+X11+X12)(X13+X14+X15)=1 • 106×(Defect Level) = 8744.76 < 9,000 • W=(Defect Level)×10,000 = $87.44

  20. The Evaluation Model with Cost Constraint • Minimize: • 106{1- Π[(ΣXiYi) (1- Σ(Xjfcj))]} • All Xi are binary numbers • Yi is the yield of the item • fcj is the fault coverage of the item • Subject to: • Π(Xi+Xi+1+....+Xi+(n-1)+Xi+n) = 1 • Cost = Σ(XiCi)+(Fine × Defect Level) < Budget

  21. An Example of Our Evaluation Model with Cost Constraint • Minimize: • 106{1-(0.85X1+0.9X2+0.93X3)(1-(0.9X8+0.95X9))(0.9X4+0.95X5)(1-(0.93X10+0.95X11+0.99X12)) (0.9X6+0.95X7)(1-(0.93X13+0.95X14+0.99X15))} • Subject to: • (X1+X2+X3)(X4+X5)(X6+X7)(X8+X9)(X10+X11+X12)(X13+X14+X15)=1 • Cost=Σ(XiCi)+(10,000× Defect Level) < $200

  22. An Example of Our Evaluation Model with Cost Constraint • The best solution of this example is (X3, X5, X7, X9, X12, X15) • Minimize: • 106{1-(0.85X1+0.9X2+0.93X3)(1-(0.9X8+0.95X9))(0.9X4+0.95X5)(1-(0.93X10+0.95X11+0.99X12)) (0.9X6+0.95X7)(1-(0.93X13+0.95X14+0.99X15))}=4643.59 • Subject to: • (X1+X2+X3)(X4+X5)(X6+X7)(X8+X9)(X10+X11+X12)(X13+X14+X15)=1 • Cost=Σ(XiCi)+(10,000× Defect Level)= $196.43< $200

  23. Outline Introduction Quality-Cost Evaluation Models Interconnect Testing Experimental Results Conclusions

  24. Motivation Since the integrated bare dies have been tested individually, the defects probably occur on the interconnect during the wire assembling Thus interconnect testing is an important step after the whole design is packaged

  25. Our Approach Even the bare dies are designed without boundary scan, we still can detect the fault by fault simulation The bare die is like a black box, and we do not know the architecture of it. We just observe the value from the I/O of the circuit

  26. Fault Simulation • Simulate circuits which are fault-free and faulty, then check the result of POs to determine the fault is detected or not • Given these elements, we can determine the fault coverage and undetected fault of this design • Circuits • Fault model • Test pattern

  27. Fault Model • A fault model is an engineering model to describe the fault, and the designer can know the consequence of the fault from the fault model • Two fault models are used in our example • Stuck-at fault model • Misplaced fault model

  28. An Example of Stuck-at Fault Model 1 1 1 S27(1) jc2 S27(2) 0 0 0 1 POs 0 1 PIs 0 1 0

  29. An Example of Stuck-at Fault Model Stuck-at zero 1 0 0 S27(1) jc2 S27(2) 1 0 0 0 POs 0 1 PIs 0 1 0

  30. An Example of Misplaced Fault Model 1 0 1 PIs jc2 C17 S27 0 0 0 0 POs 1 1 0 1 1 1 1 1 1

  31. An Example of Misplaced Fault Model Misplaced fault ! 1 0 0 PIs jc2 C17 S27 0 1 0 0 POs 0 1 0 0 1 1 1 1 1

  32. Outline Introduction Quality-Cost Evaluation Models Interconnect Testing Experimental Results Conclusions

  33. The experimental environment Implement (within SIS environment) on a Linux platform (CentOS release 4.4) with a 3.0GHz machine and 32GBytes memory We connect several circuits to simulate an SiP design, and apply 10,000 random patterns on this SiP design

  34. Experimental Results of Our Quality-Cost Evaluation Models

  35. The Detailed Data of Our Testbench of Interconnect Testing

  36. The Detailed Data of Our Testbench of Interconnect Testing

  37. Experimental Results of Interconnect Testing with Stuck-at Fault Model

  38. Experimental Results of Interconnect Testing with Stuck-at Fault Model

  39. Experimental Results of Interconnect Testing with Misplaced Fault Model

  40. Experimental Results of Interconnect Testing with Misplaced Fault Model

  41. Outline Introduction Quality-Cost Evaluation Models Interconnect Testing Experimental Results Conclusions

  42. Conclusions • We propose an approach to find a solution to • Reduce the cost of the SiP and keep its quality • Improve the quality of the SiP and control the budget • Even the bare dies are no boundary scan, the fault still can be detected in our approach, and do not alter the original design

  43. Thank you

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