Abstract & Main Goal

1. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract & Main Goal The focus of this project was the creation of an analyzing device for a std. PCI-Express (1.0) communication line at speeds of 2.5Gb/sec. by means of a VHDL core on a Xilinx “Virtex II pro” FPGA platform. The core implements Real Time Hardware based algorithms and enables the user to monitor and analyze PCI-Express transactions using a simple register based interface .

2. Signaling Rate [Ghz] PCI-Express 3rd Generation I/O Serial Protocol 15 10 5 Parallel Bus limit 1 ~ ~ PCI Parallel ISA Parallel 1980’s 1990’s 2000’s High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Architecture Development

3. Switched Fabric Arch BUS Arch CPU CPU PCI Express GFX Host Bridge Memory AGP GFX Memory Root Complex PCI Bridge PCI-X Bridge Switch Switch Switch PCI-X Bridge PCI Bridge PCI Bridge PCI-X Device PCI-X Device Legacy End point End point PCI-X Device PCI-X Device End point Legacy End point PCI PCI High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Classic PCI Vs

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות PCI-Express - Architecture Dual SimplexDifferential2.5 Gbps/directionSeparate clock ! x1 Lane Wide Link Switch Operation Traffic Direction End Point End Point

5. Transaction Data Link Physical High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות PCI-Express - Protocol • Memory • I/O • Configuration • Message Split Transaction - Request/Complete 3 Layers

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות R&D – Signal Integrity • System Under Test Digital signal requirements : • Complete and Unimpaired • Accurate placement in time • Stable, valid logic levels • Clean, fast transitions • Transient free Analyzers offer a vital validation Tool !

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות R&D – Data Integrity • System Under Test Data Packets requirements : • Complete & Unimpaired • Protocol Compliant • Valid structures • Valid symbols • Error free Data Integrity is the main focus of this project !

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Analyzers - Market Survey • Algorithms – Software manifested • Offline filtering - Storage Limit • Stand alone Tool • No open source • High Cost – 30,000 $

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Goals • Standard Hardware – Low Cost • Low Storage Demand • PCIe (1.0) Compliant • Bit Level Filtering Control • Simple User Friendly Interface • Educational Merits – Lab Experiment

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Overcoming Technical Hardships • Real Time Algorithms • High Speed Synchronization • Data Masses Handling • Decryption and Descrambling • Extensive Spec Survey

11. A B Mother Board Stub Switch Header Header High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות PCI-Express Analyzer • Line Sniffing • Data Sampling • Analyzing and Filtering • Displaying Results PCI-Express Analyzer

12. Transaction Data Link Physical Gigabit Receiver 1 Decryption Module 2 Physical Data Link Wrap Filter 3 Packet Filter 4 Central Controller Memory Controller 7 8 MSU Control 5 Link Assessment 6 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות PCIe Analyzer –Arch. Physical Physical 4 3 7 Transaction 2 8 5 Physical 6 1

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Originality • Minimized – Synthesis Oriented Programming • Unique Algorithm Development • Mathematical – Logical Solutions • Optimized Performance • Code - 10,000 Lines Open Source • Embedded PCIe Generator

14. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Innovation • Minimization - Entire System on Single Chip • Unique Tool using Standard Hardware (300$) • Minimal Resources yield Maximal Result • Real Time Hardware Processing • Open Code flexibility • Embedded into System under Test

15. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות PEAC – TOP Block Diagram

16. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Development Process Semester A Semester B High Speed Communication Fundamentals Constructing Analyzer Core Building Blocks PCI Express Architecture Concepts Debugging & Testing Each block market survey Current Available Products Final Core Integration Existing Infrastructure Analyzer Core Development report Final Concept Requirements Doc

17. Traffic Analyzer Core הטכניון - מכון טכנולוגי לישראל Technion - Israel institute of technology Kasher Award Finals Performed by : Samuel Amir , Danny Volkind Instructed by : Mr. Orbach Mony Assisted by : Mr. Eli Shosan