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PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS. BARIS TASKIN AND IVAN S. KOURTEV. UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING. Outline. Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions.

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PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

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  1. PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS BARIS TASKIN AND IVAN S. KOURTEV UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING

  2. Outline • Introduction • Timing Constraints • LP Model Formulation • Experimental Results • Conclusions

  3. Introduction • Large-scale SOC • Time borrowing (cycle stealing) • Clock skew scheduling • Clock/Timing schedule • Minimum clock period

  4. Background • Local data path • Graph

  5. Latch Operation Positive level-sensitive

  6. Time Borrowing Higher Operating Frequency! Flip-Flop based Latch based

  7. Clock Skew Tskew(i,f) = ti - tf Clock signal delay at the initial register Clock signal delay at the final register

  8. Clock Skew Scheduling Higher Operating Frequency! Zero clock skew Non-zero clock skew

  9. Optimization Problem Time borrowing + Clock skew scheduling • Latch-based • Non-zero clock skew • Flip-flop-based • Zero clock skew

  10. Timing Parameters

  11. Outline • Introduction • Timing Constraints • LP Model Formulation • Experimental Results • Conclusions

  12. Constraints Constant or Variable?

  13. af Af Latching Constraints

  14. Synchronization Constraints

  15. Synchronization Constraints Max!

  16. Propagation Constraints Min! Max!

  17. Outline • Introduction • Timing Constraints • LP Model Formulation • Experimental Results • Conclusions

  18. Problem Formulation

  19. Modified big M (MBM) Method

  20. M MBM Method Example +1000c C1a: ca C1b: cb b c c a NON-LINEAR LINEAR

  21. LP Model Formulation [Synchronization Constraint-I]

  22. Implementation and Model Highlights • C++ implementation • Off-shelf optimizer (CPLEX) • Provide stand-alone model • Robust, fast • Sensitivity analysis

  23. Outline • Introduction • Timing Constraints • LP Model Formulation • Experimental Results • Conclusions

  24. Timing Analysis OUTPUT INPUT

  25. Example

  26. Additional Constraints Clock signal delays at R1 and R4 Clock Pin Circuit C tR1 = tR4 = c c:constant R2 R5 R1 R3 ... R4

  27. ISCAS’89 Benchmark Results

  28. Outline • Introduction • Timing Constraints • LP Model Formulation • Experimental Results • Conclusions

  29. Conclusions • Increased performance • Time borrowing • Clock skew scheduling • Complete framework for timing analysis • Multi-phase synchronization

  30. PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS QUESTIONS BARIS TASKIN AND IVAN S. KOURTEV UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING

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