Parallel Optimization Tools for High Performance Design of Integrated Circuits

1. Parallel Optimization Tools for High Performance Design of Integrated Circuits Azadeh Davoodi Assistant Professor (joint work with my student Tai-Hsuan Wu) Department of Electrical and Computer Engineering WISCADVLSI Design Automation Lab http://wiscad.ece.wisc.edu Thanks to: Jeff Linderoth

2. 120% 100% 80% Profit 60% 40% 20% 0% 0 3 6 9 12 15 -20% Months Late Research: Optimality in IC Design “Optimality matters to shorten the design cycle of Integrated Circuits and meet stringent time-to-market requirements.” Source: MIPS Technologies Optimality: • required to assess the quality of existing design techniques • currently use heuristics to solve large-scale, non-linear and discrete optimization problems • have no idea how far might be from the optimal solution

3. sL sH k1 sL sH sL sH k2 k3 ... ... Kn-1 ... Kn 2n Optimization for High Performance Design • Discrete optimization problem • Typically the relaxed continuous version is solved as a convex program and the result is discretized j dj Tcons

4. Examples of Optimization Complexity Azadeh Davoodi--WISCAD

5. Workers W1 W2 W3 W4 Using Master-Worker Framework of Condor for Grid Optimization http://www.cs.wisc.edu/condor/mw C++ APIs which facilitate: • dynamic and opportunistic resource utilization • fault tolerant implementation via checkpointing and job migration Master Unprocessed Tasks Finished Tasks T1 T5 T2 T6 T7 T3 T4 T8 T9 Tasks in process Azadeh Davoodi--WISCAD

6. sL sH sL sH sL sH ... ... ... 2n Master-Worker Implementation for High Performance IC Design • Worker: • each worker computes upper and lower bounds for K number of nodes in the search tree sequentially and communicates the bounds to the Master Master: • imposes variable ordering in the branch-and-bound search tree • applies pruning of sub-optimal branches • check points after every 5000 completed tasks by workers

7. Dealing with Communication Overhead • 3 types of data exchange between the Master and each Worker: • scalar upper and lower bounds • circuit information (optimization problem description) • partial variable assignment • Send above only once when the worker is allocated and reuse each worker for future tasks as much as possible

8. MW Implementation in Condor MASTER SUBMIT FILE Universe   = Scheduler Executable = master_DGS_socket Image_Size = 100000 +MemoryRequirements = 100 Input   = in_master.socket Output  = out_master.socket Error  = out_worker.socket Log   = _DGS.log Requirements = (Arch == "INTEL" && OPSYS=="LINUX") getenv  = True Queue WORKER SUBMIT FILE Universe = Vanilla #Worker 1Executable= exec0.$$(Opsys).$$(Arch).exe arguments = 0 8997 8997 144.92.240.35 Log = log_file Output = output_file.0 Error = error_file.0 Requirements = ( Arch=="INTEL“ && OPSYS=="LINUX") should_transfer_files = Yes when_to_transfer_output = ON_EXIT rank = Mips on_exit_remove = false Queue #Worker 2 … • Resource Information: • 179 CAE machines Intel/Linux • If all CAE are in use, “Flocks” to the queue of Intel/Linux machines in CS Azadeh Davoodi--WISCAD

9. Results On-an-average each variable had 4.5 discrete options to choose from. Azadeh Davoodi--WISCAD

10. Future Plans • Install and work with personalized Condor • Work with larger circuits and more number of sites in addition to CAE and CS • Study possibilities for optimization on a grid of multi-core machines • Better understand and work around the priority scheduling of jobs at Condor  Azadeh Davoodi--WISCAD