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WBS 7.2 & 7.3: Data Acquisition

WBS 7.2 & 7.3: Data Acquisition. D. Casper (UC Irvine). Outline. WBS 7 Components Design Specifications Design Issues and Concerns Progress to Date and Near Term Plans Cost and Schedule Overview Cost and Schedule Issues and Concerns Conclusions. WBS 7.2 & 7.3: DAQ.

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WBS 7.2 & 7.3: Data Acquisition

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  1. WBS 7.2 & 7.3:Data Acquisition D. Casper (UC Irvine)

  2. Outline • WBS 7 Components • Design Specifications • Design Issues and Concerns • Progress to Date and Near Term Plans • Cost and Schedule Overview • Cost and Schedule Issues and Concerns • Conclusions Electronics and DAQ

  3. WBS 7.2 & 7.3: DAQ • CROCs and DAQ (7.2, 7.3) • One CROC per 48 MAPMTs • Each CROC controls 4 LVDS chains of 12 MAPMTs • Three VME crates + computer • Two crates for CROCs • One crates for auxiliary electronics • Front-end/computer interface • Distribute trigger and synchronization from NuMI • Monitor and control MAPMT high-voltages • Configure front-end electronics Electronics and DAQ

  4. Specifications • Synchronization • Measure global time (between front-end boards) to a few nanoseconds • Trigger • Tap into NuMI timing signals through MINOS • Readout • Handle rates up to 1 kHz (for PMT testing and calibration) • Control • MAPMT HV control and monitoring • Configuration of front-end board firmware Electronics and DAQ

  5. Design Issues and Concerns • CROC Design • Not technically challenging, but requires EE time • Triggering and Synchronization • Need to flesh-out interface with NuMI and MINOS • Understand what auxiliary electronics are required • Investigate possibility of self-triggering • Firmware issue? • Readout • Requirements for PMT testing unspecified • Requirements for Veto Wall unspecified Electronics and DAQ

  6. Progress to Date/Near-Term Plans • Progress • LVDS chaining tested successfully (between front-end boards only) • Protocol and Frame for LVDS communications successfully tested (Christian Gingu) • Designed to be forward compatible with full required functionality • Near Term Plans • Begin design of CROC prototype as soon as possible • Procure VME system for testing and writing low-level readout software Electronics and DAQ

  7. Cost and Schedule Overview (I) Electronics and DAQ

  8. Cost and Schedule Overview (II) • Current schedule is out of date • e.g. CROC design did not begin on 6/1/05 and will not be completed on 9/20/05 • Projected Schedule • CROCs: • Should begin design as soon as possible • Finish production and testing of prototype by July ’06 • VME Readout System • Procurement of VME test system scheduled for October 2005 • Need to complete paperwork for UC Irvine MoU, etc. Electronics and DAQ

  9. Cost and ScheduleIssues and Concerns • PMT Testing (WBS 6) Drives Our Schedule • Need to understand required components and coordinate schedules • M&S costs for CROC prototypes (7.2.3) underestimated (need more than two) • Auxiliary Electronics • MINOS timing module for NuMI synchronization not explicitly included in WBS • Veto Wall DAQ Requirements (if any) Unspecified • Electronics Design • Paul is unavailable until roughly 1/06 • Design of CROC prototype should start as soon as possible • Should request EDIA time from another EE Electronics and DAQ

  10. Conclusions • Base Cost: $349,464 (total, no contingency) • M&S: $210,310 • Labor: $139,154 • Need to update after confirming the number of prototypes needed • Highest Contingency Items: • CROC production: 50%  $48,000 = $24,000 • Need a concrete design • Other M&S contingencies are nominally 20% • Based on old quotes, need to update • Unspecified auxiliary electronics • No big-ticket items, but potentially a number of smaller ones • Schedule Risks: • CROC design should begin as soon as possible, in parallel with front-end work • Not a significant technical risk • Only serious constraint is PMT testing • Understand the WBS 6 schedule and requirements Electronics and DAQ

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