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ECE 551: Digital System Design & Synthesis

ECE 551: Digital System Design & Synthesis. Final Review. Exam Format. 2 hours Roughly 7 problems – each with multiple parts Open book & two note sheets Similar to the two previous exams posted on the course homepage Material Covered Chapters 8-10 Lecture Sets 9-14

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ECE 551: Digital System Design & Synthesis

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  1. ECE 551: Digital System Design & Synthesis Final Review

  2. Exam Format • 2 hours • Roughly 7 problems – each with multiple parts • Open book & two note sheets • Similar to the two previous exams posted on the course homepage • Material Covered • Chapters 8-10 • Lecture Sets 9-14 • Problem Set 5 and Course Project • Synopsys Tools Manuals • Working Knowledge of Material Prior to Midterm

  3. Synthesis of Combinational Logic:Tools Perspective • Basic HDL based design flows (DCUG and Ciletti - CH8) • Basic Synthesis Flows (DCUG and Ciletti - CH8) • Internal Synthesizer Flow overview • Logic Optimization (De Micheli) • Single output functions minimization – espresso (operators) • Multi-output function minimization – MIS (transformations) • Important concepts • Key steps performed in synthesis • Two-level, single-output logic operators • Expand, Reduce, Reshape, Irredundant • Multiple-level, multiple-output • Elimination, Decomposition, Extraction, Simplification, Substitution

  4. Synthesis of Combinational Logic:Coding for Synthesis • Basic Synthesis • Combinational, RTL, FSM, Behavioral (Ciletti - CH9) • Advantages/Disadvantages of Synthesis (Ciletti - CH9) • Synthesis Methodology (Ciletti – CH9) • Vendor Support (Ciletti - CH9) • Coding for Synthesis of Combinational Logic (Ciletti, GHCS) • GHCS – Guide to HDL Coding Styles for Synthesis (synco.pdf) • Basic coding of if and case statements - priority encoding • Reorder code for late arriving signals • Coding for basic building blocks • Decoder, Priority Encoder, Reduction XOR, Multiplexer • Tree versus array structures - for parameterized modules

  5. Synthesis of Combinational Logic:Coding for Synthesis • Coding for Synthesis of Combinational Logic • Datapath duplication to reduce delay • General coding style guidelines • Unintentional Latch Inference • avoid by using else, default, and synopsys full_case • Incomplete Sensitivity Lists • may lead to pre-synthesis and post-synthesis mismatches • Unnecessary Calculations in for Loops • Should be pulled out of loops • Resource Sharing • Not in conditional assignments, but in if-then-else • Optimizing Arithmetic Expressions (A + B) + (C + D) • Sharing Common Subexpressions

  6. Design Partitioning for Synthesis • Lots of information from Chapter 3 of DCUG • Design Partitioning Strategies • Partition for design reuse - document, standardize, parameterize • Keep related combinational logic together - allows better optimizations • Avoid glue logic, particularly at top level - what and why • Register block outputs - advantages vs. disadvantages • Partition by design goal - minimum area or minimum delay • Partition by compile technique - structure or flattening • Keep sharable resources together - in same always block • Keep UDRs (User-Defined Resources) with logic they drive • Isolate special functions - pads, clocks, boundary scan at top level • Place large SRAMs and DRAMS at top core level • Size blocks based on available computational resources

  7. Synthesis of Sequential Logic • UDPs – restrictions & what tools do • Latches • Edge-triggered flip-flops • Synopsys multi-bit inferences • Registered combinational logic • Shift registers and counters • Finite state machines (FSMs) • Resets • Gated Clocks • Be able to write synthesizable sequential logic code

  8. Synthesis of Language Constructs • Text (CH10) and HDL Compiler for Verilog Reference Manual (CH3-5, hdlcv.pdf) • Synthesizing nets • Synthesizing registers • Synthesis with “x” and “z” • Expressions and Operators • Arithmetic, Non-Arithmetic, Shift, Relational and Identity, Reduction, bitwise, and logical, Conditional, Concatenation • Assignments • Timing Control in Synthesis • Multiple Cycle Operations • Loops, Fork & Join, Disables • Tasks and Functions

  9. Constraints and Timing • Mostly from Design Compiler Reference Manual: Constraints and Timing (dcrm.pdf) – CH1-2 • Constraint Classification • Design Rule Constraints • Maximum Transition Time, Maximum Fanout • Maximum and minimum capacitance, Cell degradation • Optimization Constraints • Area, delay, and porosity • Constraint violations and slack time • Including defining timing paths and path delays • Setting Constraints • Constraints for realistic goals

  10. Optimization • Mostly from Design Compiler Reference Manual: Optimization and Timing (dcrmo.pdf), CH1-2 • Optimization • Phases : combinational, sequential, I/O pad, local • Logic-Level and Gate-Level Optimization • Optimization Flow • Compilation Types • Compilation Strategies

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