Three-Dimensional Microelectronics Integration: Design, Analysis and Characterization

1. Three-Dimensional Microelectronics Integration:Design, Analysis and Characterization Zeynep Dilli Ph.D. Program Dissertation Proposal

2. Introduction & Motivation: 3-D Integration • Current trend in electronics: Tighter integration at every integration level: • Device  Gate  Chip  …  Board  Main Board  System • Still Planar! • Limitations: Speed, compactness, signal clarity, robustness… • “Smart Dust” systems • Ideally self-contained, self-powered and small • May require mixed-signal integration • 3-D stacking might be the ideal answer …with sidewall connections Stacks with cap chips… …with intertier vias

3. 3-D vs. 2-D Integration: Advantages & Disadvantages • Net system size reduction • Increased active Si area/chip footprint • Delay reduction: faster clocks or higher bandwidth • Shorter interconnects • Lower parasitic & load impedance • Potential intra-system noise reduction • Potential substrate noise reduction • Heterogeneous integration • More freedom in geometric design • Lower power consumption. • Increased heat-dissipation problems • Increased design complexity. Challenge to the Designer 3-D integration is a subject that ties together chip design, chip physics, device design, circuit design, electromagnetics, and geometrical layout problems.

4. Outline • Proof of concept: A 3-D integrated self-powering system • Circuit performance in 3-D integration • Passive devices for self-contained 3-D systems

5. Self-Powered Electronics by 3-D Integration: Proof of Concept 3D system concept: Three tiers • Sensor (Energy harvesting: Photosensor) • Storage (Energy: Capacitor) • Electronics (Local Oscillator and Output Driver)

6. Process & Circuit • 0.18 μm fully-depleted SOI process • 3 metals • p-type substrate, ~1014 • Implants: Threshold adjustment, CBN and CBP (5x1017), source-drain, PSD and NSD (0.5x1019, 1x1019) ip

7. Process information • Silicon islands 50 nm thick • Three-metal process • Three tiers stacked • Through-vias • Top two tiers turned upside-down Figure adapted from MIT_LL 3D01 Run Application Notes

8. Photodiodes: Design Issues • Major problem: The material depth is very small • Photocurrent=Responsivity [A/W] x Incident Power • Responsivity= Quantum efficiency x λ[μm] /1.24 • For red light, λ[μm] /1.24 = 0.51 • Incident Power = Intensity [W/μm2] x Area [μm2] • Sunlight intensity ≈ 1x10-9 W/μm2 • Quantum Efficiency: η = [# electron-hole pairs]/ [# incident photons] • Depends on reflectance, how many carrier pairs make it to the outer circuit, and absorption • At 633 nm (red light), absorption coef. ≈3.5e-4 1/nm  amount of photons absorbed in 50 nm depth is (1-exp(-αd))≈ 0.017 • η = 0.017 x reflectance x ratio of non-recombined pairs ≈ 0.017 x 0.75=0.013 •  Photocurrent=0.013 x0.51 x 1x10-9 x Area[μm2] = 6.63 pA/μm2

9. Photodiodes: Design Issues  Photocurrent=0.013 x0.51 x 1x10-9 x Area[μm2] = 6.63 pA/μm2 • Photosensitive area: pn-junction depletion region width (Wd) times length • Available implants: Body threshold adjustment implants (p-type CBN and n-type CBP, both 5x1017 cm-3); higher-doped source-drain implants and capacitor implants; undoped material is p-type, ~1014 cm-3. • Two diode designs: CBN/CBP diode and pin diode (CBP/intrinsic junction) • CBN/CBP diode Wd=0.0684 μm; A=0.5472 μm2 • Pin-diode Wd ≈ 1.5 μm; A=15 μm2; possibly problematic • To increase: Higher-intensity light; optimal wavelength (higher wavelength increases λ/1.24, but decreases absorption) Layout Constraints: As many diodes as possible; diodes in regular arrays; need three bonding pads of a certain size; assigned area 250 μm by 250 μm only Layout: 2062 CBN/CBP diodes: 7.48 nA; 52 pin diodes: 5.17 nA  Expect about 12 nA

10. Photodiodes: CBN/CBP Diode Layout

11. Photodiodes: pin diode layout

12. Layout: Tier 3, Diodes and Pads “VDD” “GND” Oscillator output

13. Layout: Tier 2, Capacitor Top plate: Poly Bottom plate: N-type capacitor implant, CAPN Extracted value: 29 pF Expected value: 30 pF

14. Layout: Tier 1, Local Oscillator

15. Circuit Operation • Cstorage is charged up to a stable level depending on iph.

16. Circuit Operation • Vrail=270 mV, fosc=1.39 MHz for iph=15 nA.

17. 3-D System, Further Research, 1 • Test the device once fabrication is completed: • Self-contained system, 250 μm x 250 μm x 700 μm • Design a version to be fabricated at LPS • Greater active photosensor depth • Voltage regulator to prevent diode forward bias current overtaking the photocurrent • Investigate rectifying antennas as alternate power source • Preliminary investigation done on circuit board level • See further work on passive structures

18. 3-D System, Further Research, 2 • Compare yield of 3-D system with planar system of the same footprint area • Codify self-powering system design methodology • Photodiode-based: • Photodiode power generation ability: Diode design and chip optical design (microlenses/AR coatings…) • Charge storage system: Capacitor, high-k dielectric use • Power regulation circuit requirement • Rectifying-antenna based: • Antenna properties: Possible low-k dielectric use • Need for a transformer • Rectifier diode design • Tied to load circuit characteristics

19. Outline • Proof of concept: A 3-D integrated self-powering system • Circuit performance in 3-D integration • Passive devices for self-contained 3-D systems

20. 3-D Integration: Performance Study • Speed • Intra-chip communication • Heat • Generation and dissipation • Noise • Substrate noise • External Interference • Signal Integrity • Compare performance with planar integrated circuits and connections

21. Internal Osc. External Osc. One-stage delay 112 MHz (31-stage) (equivalent to 1.16 GHz for 3 stages) 398 KHz (11-stage) (equivalent to 1.46 MHz for 3 stages) ~330 ps for internal, ~330 ns for external dev. Performance: Speed • Bonding pads, wires: Extra load + parasitics: Slow things down Left: “External” ring oscillator, 11 stages (two stages are shown) Right: Internal ring oscillator, 31 stages, output to divide-by-64 counter Both are comprised of minimum-size transistors, simulated speed for 31 stages: 132 MHz. Speed ratio: 794.5 Load ratio: ~1000

22. 3-D Connections vs. Planar Off-chip Connections Chip-to-chip communication between different chips with vertical vias that require 12m x 12m metal pads Cadence-extracted capacitance for a pad 9.23 fF: Same order of magnitude as inverter load cap in2 out2 out1 in1

23. 3-D Connections: “Symmetric” Chip Structures that can be connected in 3D and planar counterparts for comparison

24. 3-D Connections: “Symmetric” Chip • A 31-stage planar ring oscillator and • A 31-stage 3-D ring oscillator (In the figure, groups of 5-5-5-5-5-6). The proper pairs of pads have to be connected to each other through vertical through-chip vias post-fabrication for the circle to close. Simulation results: Planar: 142 MHz 3-D, six “layer”s: 122 MHz (six vertical pads as extra load) To counter input “symmetry” axis

25. 3-D Integration: Performance Study • Speed • Intra-chip communication • Heat • Generation and dissipation • Noise • Substrate noise • External Interference • Signal Integrity • Compare performance with planar integrated circuits and connections

26. Performance: Heat • Coupled simulation at device and chip level to characterize chip heating: Generation, distribution and dissipation

27. Performance: Heat Modified heat flow equation: Integrated over a volume to obtain a “KCL” eqn.: “C(dV/dt) + (V2-V1)/R = I” Discretized: General Algorithm: Solve device equations for a range of temperatures; set up the chip thermal network including heat generation; assume initial temperatures and solve the thermal network; obtain heat generated by each transistor at that temperature; reevaluate heat generated by each transistor, repeat until convergence Also Possible: Use solver to suggest layout solutions for heat dissipation

28. Performance: Heat • Device operation characteristics depend on temperature (e.g. I-V characteristic of a diode) • Affects circuit operation (e.g. foscof a ring oscillator)

29. 3-D Integration: Performance Study • Speed • Intra-chip communication • Heat • Generation and dissipation • Noise • Substrate noise • External Interference • Signal Integrity • Compare performance with planar integrated circuits and connections

30. Performance: Noise • Substrate Noise • Modeled as substrate currents [1] or lumped-element networks [2] • Characterized with test circuits [3] or S-parameter measurements [4] [1] Samavedam et al., 2000 [2] Badaroglu et al., 2004 [3] Nagata et al., 2001, Xu et al., 2001 [4] Bai, 2001

31. Performance: Signal Integrity • On-chip interconnects on lossy substrate: capacitively and inductively coupled [1] • Characterized with S-parameter measurements • Equivalent circuit models found by parameter-fitting [1] Zheng et al, 2000, 2001; Tripathi et al, 1985, 1988…

32. Performance: Signal Integrity • Substrate properties and return current paths affect interconnect characteristics • Three modes of operation, affecting loss and dispersion [1] • Mutual inductance from a return current with a complex depth to calculate interconnect p.u.l inductance [2] • Effect of a second substrate stacked in proximity not investigated • Effect of vertical interconnects not investigated [1] Hasegawa et al, 1971 [2] Weisshaar et al, 2002

33. Performance: Further Research, 1 • Speed:3-D integrated chip in design revision • Heating:Planar heating characterization chip in fabrication; 3-D heating characterization chip being designed • Noise:Design a planar chip to model and characterize the substrate noise coupling within; design a 3-D integrated chip to compare noise performances

34. Performance: Further Research, 2 • Signal Integrity: Adapting the heat-elements network to coupled interconnect models • Evaluate the sensitivity of different interconnect layouts to external pulses • Set up a coupled network • Use random current sources as external pulses to generate a coupling map • Design interconnect chips for experimental verification • Interconnect equivalent circuit model/parameter alterations for 3-D integration • Investigate capacitive and inductive coupling to a nearby conductive, electrically disconnected substrate in addition to the associated substrate • Derive transmission line parameters • Design chips for experimental verification

35. Outline • Proof of concept: A 3-D integrated self-powering system • Circuit performance in 3-D integration • Passive devices for self-contained 3-D systems

36. On-Chip Inductors and Transformers • Self-contained integrated systems may require passive structures: • Communication with other units in the network: on-chip antennas • Power harvesting: Rectifying antennas and transformers • Various analog circuits---mixers, tuned amplifiers, VCOs, impedance matching networks: Inductors, transformers, self-resonant LC structures

37. On-Chip Inductors and Transformers • Trace separation • Metal layer • Substrate doping • Substrate shields • Stacked or coiled structure • Planar inductor design • Number of turns • Total length • First/last segment length • Trace width • Planar inductor modeling • Define an equivalent circuit, parameter-match to measurements • Separate physics-based approaches for serial or shunt parameters

38. De-embedding and Extraction An on-chip inductor has frequency ranges where it behaves inductively or capacitively: ----DUT---- -----Ref. frame after Open is taken out------- --------Measured reference frame for DUT_full------------

39. A Qualitative Look at the Inductance Curve

40. On-Chip Inductors: Measurements

41. Different Metal Layers M3: Lowest capacitance, highest Q factor

42. Planar vs. Stacked Inductors 58072 micron2vs. 22500 micron2

43. Transformers

44. Tuning an Inductor with Light Bottom right: Shunt capacitance increases; fsr drops ~150-200 MHz Top right: Substrate resistance decreases: peak impedance increases

45. Exploiting Self-Resonance • Certain circuits need LC tanks • Mixers, tuned LNAs (as a tuned load) • LC filters • There is some interest on intentionally integrating inductors with capacitors to obtain an LC tank • Use the equivalent circuit model in a circuit design to exploit this effect and investigate optimization; verify experimentally

46. Passives: Further Research • 3-D inductors in chip stacks • Investigate multiple-substrate inductor geometries • Electromagnetic modeling, experimental verification • Low-k dielectrics • Tunable Self-Resonant Structures • Controlled tuning methodology • Photoelectrical • Electrical • Electromagnetic • Circuit applications

47. Summary • 3-D Self-contained System Design • 3-D System Performance Analysis • Speed • Heat • Noise • Signal integrity • Passive Structures for Self-Contained Systems • 3-D passives • Tunable passives

48. …And on another track… • Engineering education research • Past work: • Helped direct ECE program for Maryland Governor’s Institute of Technology program, Summer 2001 • Co-authored textbook • Benjamin Dasher Best Paper Award in FIE 2002 • Contributed to the design of ENEE498D, Advanced Capstone Design • Presented paper in ITHET 2004 • Participated in departmental outreach programs • GE program for high school teachers, MERIT students, WIE summer programs • Attending PHYS 708: Physics Education Research Seminar • Engineering education is an open research field as well • Considering several questions adapted from PER: Student knowledge body characterization; concept lists for EE…