Catholic University, PUCRS (Brazil) Faculty of Informatics and Faculty of Engineering

1. S G E Catholic University, PUCRS (Brazil) Faculty of Informatics and Faculty of Engineering Embedded Systems Research Group <http://www.inf.pucrs.br/gse> “CCSDS TC/TM Interface Targeting Reconfigurable Logic” by Eduardo Augusto Bezerra CTA/ITA, São José dos Campos, 23-24 November 2004.

2. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

3. S G E Supporting Team: The GSE Group Application Area Emphasis: embedded software and hardware for sensors and dedicate computing systems Research Emphasis: Embedded Systems Space Systems Mobility and Pervasive Computing Precision Farming

4. Supporting Team: The Space Science Centre

5. Modular Reconfiguration Parameterisable IP Construction Supporting Team: The GAPH Group Application Area Emphasis: Telecom Systems Research Emphasis: SoC Modelling, design and validation at systemic levels Modular Systems Construction IP Construction Reconfigurable Hardware Construction Hardware Virtualisation IP cores Reconfigurable Systems

6. Supporting Team: Collaborators The University of Sussex (UK) Space Science Centre, EIT http://www.sussex.ac.uk/space-science Faculty of Engineering, PUCRS Systems, Computing and Communications Group http://www.ee.pucrs.br/~sisc IPCT, PUCRS Microgravity Laboratory http://www.ipct.pucrs.br/~microg Faculty of Informatics, PUCRS Hardware Design Aid Group http://www.inf.pucrs.br/~gaph

7. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

8. Motivation, Objectives and Contributions • Brazilian space program is interested in the use of FPGAs for the implementation of on-board processing systems; • Main objective: Design and implementation of a CCSDS telecommand and telemetry system in an FPGA; • Investigation of the use of configurable computing (FPGAs) to substitute the traditional approach (microprocessors) employed in the design of on-board computers;

9. Motivation, Objectives and Contributions • Development of a configurable system to be used in space applications; • Investigation of high level languages for hardware description (e.g. Java, C++); • Investigation/definition of fault-tolerance strategies for configurable computers; • High performance with low clock and less power consumption;

10. Motivation, Objectives and Contributions • Flexibility of developing hardware in a similar way as SW (bug fixes, system upgrades), with no HW changes; • Microprocessors: applications have to adapt to the architecture available. FPGAs: architecture adapts to the application; • Flexibility to define as many independent memory modules (distributed memory) as necessary, reducing the von Neumann bus bottleneck; • Modern FPGAs have architectures suitable for arithmetic and DSP applications.

11. Motivation, Objectives and Contributions • HW/SW co-design is too complex  investigation of pure hardware solutions. Modelling/System Description ( SystemC , SDL, CSP, Java, ...) Validation (Co - Simulation, Formal Verification) HW/SW Partitioning HW (HDL, occam) SW (C, occam) Co - Synthesis Synthesis Compilation Prototiping Software components Hardware (Library) components FPGA FPGA FPGA µ P (IP cores) FPGA analogic memory memory SoC

12. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

13. Design Decisions: The Simulation Environment Prototyping platform selection: target FPGA, prototyping board, hardware description language, …

14. Design Decisions: The Description Language Issue • The first activity in a project should be to identify the problem’s complexity. • In complex (and large) projects, the solution will certainly involve some sort of systemic approach. • In mid-size projects a behavioural HDL solution may be sufficient. • In small projects a schematic entry or structural HDL solution may be a better option, but just in cases where designers have a hardware background.

15. Design Decisions: Target Device Selection • Manufacturers of military and/or rad-hard FPGA devices: • Actel Corp. <http://www.actel.com> • Altera Corp. <http://www.altera.com> • Atmel Corp. <http://www.atmel.com> • Chip Express <http://www.chipexpress.com> • Gatefield Corp. <http://www.gatefield.com> • Lucent Corp. <http://www.lucent.com/micro/fpga> • Mission Research Corp. <http://www.mrcabq.com> • Quicklogic Corp. <http://www.quicklogic.com> • Xilinx Corp. <http://www.xilinx.com>

16. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

17. Design Methodology and Strategy • CCSDS • Consultative Committee for Space Data Systems • Employed in a large number of scientific and commercial spacecraft. • Allows reduced costs for on-board, ground and test equipment, as well as for spacecraft testing in in-orbit operation. • Standard space industry communication protocol. Frame Processing Telecommand Transmit Telecommand Receive Frame Processing Telemetry Receive R-S Decoder R-S Encoder Telemetry Transmit Space Segment Ground Segment

18. Design Methodology and Strategy FPGA AMBA bus Leon 2 Sparc V8 microprocessor HurriCANe CAN interface First step: A soft core microprocessor (Leon 2) runs a minimal CCSDS TC/TM implementation. The system uses the AMBA bus for cores’ interconnection, and a CAN core for connecting external modules.

19. Design Methodology and Strategy FPGA ? ? ? AMBA bus Leon 2 Sparc V8 microprocessor HurriCANe CAN interface End objective: Selection of some modules of the protocol suitable for HW implementation. The modules should be designed as peripherals for the Leon microprocessor.

20. Design Methodology and Strategy

21. Design Methodology and Strategy

22. Design Methodology and Strategy

23. Design Methodology and Strategy Dependability Improvement Signature Analysis-Driven Refresh Without FPGA Replication

24. Design Methodology and Strategy Dependability Improvement Masking Connectivity Faults

25. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

26. Drawbacks • Synthesis tools for high level languages are still inefficient; • VHDL is device independent, but it is not synthesis tool independent; • For good results, the designer is required to have a good knowledge of the FPGA architecture, synthesis tools functionality, and how to program in HDL for synthesis; • An acceptable VHDL description, suitable for synthesis, is in a level of abstraction lower then Assembly language, since the designer has to think in terms of flip-flops and multiplexers; • FPGAs are still expensive; • Skillful people in this field is hard to find.

27. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

28. Conclusions • The proposed project is feasible, but the right personal must be found; • A close contact with Surrey and Sussex Space groups is important for the project success; • The whole CCSDS TM/TC interface is not proper for a pure hardware implementation; • In a first moment, the whole system will be prototyped in an FPGA as a pure software implementation for a soft core RISC microprocessor; • Gradually, modules of the system will be converted into hardware as IP cores.

29. Summary • Supporting Team: GSE and Collaborators • Motivation, Objectives and Contributions • Design Decisions • Design Methodology and Strategy • Drawbacks • Conclusions • Contact Details

30. Contact Details Eduardo Augusto Bezerra Embedded Systems Research Group (GSE) Faculdade de Informática, PUCRS Av. Ipiranga, 6681, Porto Alegre, RS, Brazil Email: bezerra@inf.pucrs.br Web: http://www.inf.pucrs.br/~eduardob Web: http://www.inf.pucrs.br/gse Tel.: +55 (51) 3320 3611 or +55 (51) 3320 3695

31. Useful Links CCSDS: http://www.ccsds.org Sussex University: http://www.sussex.ac.uk/space-science Surrey University: http://www.ee.surrey.ac.uk/SSC/ SSTL: http://www.sstl.co.uk/ SatServ: http://www.satserv.nl ESA: http://www.esa.int Leon: http://www.gaisler.com/products/leon2/leon.html GSE: http://www.inf.pucrs.br/gse