EE 122: Router Design

1. EE 122: Router Design Kevin Lai September 25, 2002

2. . . . . . . Routers • A router consists • A set of input interfaces at which packets arrive • A set of output interfaces from which packets depart • Some form of interconnect connecting inputs to outputs • Router implements two main functions • Forward packet to corresponding output interface • Manage bandwidth and buffer space resources laik@cs.berkeley.edu

3. What a Router Looks Like Cisco GSR 12416 Juniper M160 19” 19” Capacity: 160Gb/sPower: 4.2kW Capacity: 80Gb/sPower: 2.6kW 3ft 6ft 2ft 2.5ft Slide by Nick McKeown laik@cs.berkeley.edu

4. Why Understand Router Design • Many companies make switches and routers • e.g., Cisco, Juniper, Nortel • Many other devices have a similar structure • e.g., PC’s internal interconnect, multi-processor interconnect • Switch design dictates what can be done at higher layers • e.g., per flow state is expensive,the need to minimize per packet processing time laik@cs.berkeley.edu

5. Why Do We Need Faster Routers? • To prevent routers becoming the bottleneck in the Internet. • To increase POP capacity, and to reduce cost, size and power. laik@cs.berkeley.edu

6. Why we Need Faster Routers 1: To prevent routers from being the bottleneck Packet processing Power Link Speed 10000 1000 2x / 18 months 2x / 7 months 100 Fiber Capacity (Gbit/s) 10 1 1985 1990 1995 2000 0,1 TDM DWDM Source: SPEC95Int & David Miller, Stanford. laik@cs.berkeley.edu Slide by Nick McKeown

7. POP with smaller routers • Ports: Price >$100k, Power > 400W. • It is common for 50-60% of ports to be for interconnection. Why we Need Faster Routers 2: To reduce cost, power & complexity of POPs POP with large routers laik@cs.berkeley.edu Slide by Nick McKeown

8. Requirements • Power • generates heat, costs money • < 5kW • Size • space costs money • < 2m3 • Bandwidth • Ports • number of external links • Price • Some customers want • Multicast • Quality of Service laik@cs.berkeley.edu

9. Generic Router Architecture • Input and output interfaces are connected through an interconnect • A interconnect can be implemented by • Shared memory • low capacity routers (e.g., PC-based routers) • Shared bus • Medium capacity routers • Point-to-point (switched) bus • High capacity routers input interface output interface Inter- connect laik@cs.berkeley.edu

10. CPU Buffer Memory Route Table CPU Line Interface Line Interface Line Interface Memory MAC MAC MAC Typically <0.5Gb/s aggregate capacity First Generation Routers Shared Backplane Line Interface Slide by Nick McKeown laik@cs.berkeley.edu

11. Fwding Cache Second Generation Routers CPU Buffer Memory Route Table Line Card Line Card Line Card Buffer Memory Buffer Memory Buffer Memory Fwding Cache Fwding Cache MAC MAC MAC Typically <5Gb/s aggregate capacity Slide by Nick McKeown laik@cs.berkeley.edu

12. Fwding Table Third Generation Routers Switched Backplane Line Card CPU Card Line Card Local Buffer Memory Local Buffer Memory Line Interface CPU Routing Table Memory Fwding Table MAC MAC Typically <50Gb/s aggregate capacity Slide by Nick McKeown laik@cs.berkeley.edu

13. Speedup • C – input/output link capacity • RI – maximum rate at which an input interface can send data into interconnect • RO – maximum rate at which an output can read data from interconnect • B – maximum aggregate interconnect transfer rate • Interconnect speedup: B/C • Input speedup: RI/C • Output speedup: RO/C input interface output interface Inter- connect C RI RO B C laik@cs.berkeley.edu

14. Typical Functions Performed by Input Interface on Data Path • Packet forwarding: decide to which output interface to forward each packet based on the information in packet header • examine packet header • lookup in forwarding table • update packet header laik@cs.berkeley.edu

15. Typical Functions Performed by Output Interface • Buffer management: decide when and which packet to drop • Scheduler: decide when and which packet to transmit Buffer Scheduler 1 2 laik@cs.berkeley.edu

16. Typical Functions Performed by Output Interface (cont’d) • Packet classification: map each packet to a predefined flow/connection (for datagram forwarding) • use to implement more sophisticated services (e.g., QoS) • Flow: a subset of packets between any two endpoints in the network flow 1 Classifier flow 2 Scheduler 1 2 flow n Buffer management laik@cs.berkeley.edu

17. Interconnect • Point-to-point switch allows to simultaneously transfer a packet between any two disjoint pairs of input-output interfaces • Goal: come-up with a schedule that • Provide Quality of Service • Maximize router throughput • Challenges: • Address head-of-line blocking at inputs • Resolve input/output speedups contention • Avoid packet dropping at output if possible • Note: packets are fragmented in fix sized cells at inputs and reassembled at outputs laik@cs.berkeley.edu

18. Output Queued (OQ) Routers • Only output interfaces store packets • Advantages • Easy to design algorithms: only one congestion point • Disadvantages • Requires an output speedup of N, where N is the number of interfaces  not feasible input interface output interface Backplane RO C laik@cs.berkeley.edu

19. Input Queueing (IQ) Routers • Only input interfaces store packets • Advantages • Easy to built • Store packets at inputs if contention at outputs • Relatively easy to design algorithms • Only one congestion point, but not output… • need to implement backpressure • Disadvantages • Hard to achieve utilization  1 (due to output contention, head-of-line blocking) • However, theoretical and simulation results show that for realistic traffic an input/output speedup of 2 is enough to achieve utilizations close to 1 input interface output interface Backplane RO C laik@cs.berkeley.edu

20. Cannot be transferred because is blocked by red cell Cannot be transferred because output buffer overflow Head-of-line Blocking • The cell at the head of an input queue cannot be transferred, thus blocking the following cells Input 1 Output 1 Input 2 Output 2 Input 3 Output 3 laik@cs.berkeley.edu

21. A Router with Input QueuesHead of Line Blocking The best that any queueing system can achieve. laik@cs.berkeley.edu Slide by Nick McKeown

22. Solution to Avoid Head-of-line Blocking • Maintain at each input N virtual queues, i.e., one per output Input 1 Output 1 Output 2 Input 2 Output 3 Input 3 laik@cs.berkeley.edu

23. Combined Input-Output Queueing (CIOQ) Routers • Both input and output interfaces store packets • Advantages • Easy to built • Utilization 1 can be achieved with limited input/output speedup (<= 2) • Disadvantages • Harder to design algorithms • Two congestion points • Need to design flow control input interface output interface Backplane RO C laik@cs.berkeley.edu