Low Power FPGAs in Wireless Sensor Networks

1. Institute for Software Integrated SystemsVanderbilt University Low Power FPGAs in Wireless Sensor Networks Peter VolgyesiResearch Scientist Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

2. WSN Projects with FPGAs • Several WSN applications with FPGA-based sensor boards: • Shooter localization • Bridge (structural) monitoring • Vehicle tracking • RF localization • Our approach: • Mote (mica2, xsm, micaz, telos, iris): RF communication • FPGA: signal processing • Relatively low-speed interface (I2C) + real-time handshaking • Sensors (audio, acoustic emission) Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

3. Shooter localization • Acoustic sensing: • Muzzle blast • Shockwave • Shooter localization • Trajectory estimation • Caliber and weapon type classification • Requirements: • High sampling rate: SW length, TDoA • Multiple channels: TDoA http://www.isis.vanderbilt.edu/projects/countersniper Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

4. Shooter Localization • Initially on mica2 nodes with single mics • Signal processing on the uC • Several FPGA-based multi-channel sensor boards with motes • Experimenting with DSP processors • Did not scale well with the number of channels • Currently: FPGA-based 8 channel integrated board • Multiple channels are processed at 1MSPS while the FPGA is running only @ 20MHz. Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

5. Shooter Localization Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

6. Bridge Monitoring • Acoustic emission sensors • Detecting and localizing cracksin steel bridge elements • On-demand inspection and/or continuous monitoring. • Low power requirements andvery high sampling rate • 4 channels @ 3.5 MSPS • FPGA runs @ 7MHz • First design using low-power FPGA Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

7. Vehicle Tracking - Beamforming • Beamforming on 4 channels • 100 kSPS • 36 beam angles in parallel • Multiple source tracking • PSD estimation • 1 Hz resolution • DC-2kHz • PSD compression • FPGA runs @ 20MHz Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

8. FPGA Basics • Programmable logic: • Combinational logic • flip-flops (registers) • routing • Building blocks: • Programmable interconnect • Logic blocks (logic, regs) • I/O blocks • Clock networks and PLLs/DCMs • Block memory • Other hardware macros: multipliers, DSP blocks • Programming / debugging interface (JTAG, PROM) Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

9. FPGA Technologies • SRAM-based (mainstream) • Logic functions: SRAM LUTs (4, 6 inputs) • Storage elements: SRAM flip-flops • Interconnect: SRAM-controlled switches, muxes • Configuration(LUTs, interconnect): loaded from external storage Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

10. FPGA Technologies Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS • Flash-based • Logic functions: switches • Storage elements: feedback loops • Interconnect: flash-controlled switches, muxes • Antifuse • One time programmable

11. FPGA Market • Design Tools • VHDL, Verilog, IP cores • Device manufacturers provide low cost (free) tools • Expensive 3rd party tools for complex designs (ASIC background) • Mentor Graphics • Synplicity • Magma, Altium, Cadence Device manufacturers (employees, revenue) • Xilinx (3000, $2billion) • SRAM FPGAs, CPLDs • Altera (2800, $1.5billion) • SRAM FPGAs, CPLDs • Lattice (600, $250million) • SRAM FPGAs, CPLDs • Actel (500, $200million) • Flash-based FPGAs • Antifuse, radiation hardened devices • Mixed signal programmable devices • Quicklogic (150, $34million) • Antifuse devices • SiliconBlue • Low-power SRAM FPGAs • Anchronix • High-speed SRAM FPGAs Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

12. CMOS Trends – FPGA perspective • Currently it seems easier to decrease the transistor size (process node) than increase the operating speed. • Transistor count per die area still grows exponentially • FPGAs can take advantage of this easily • Processors (controllers, DPSs) do not • Multiple cores • Pentium IV (Netburst) “fiasko” • Power, price, size can be scaled much better to the application Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

13. Drawbacks of Mainstream FPGAs Power consumption (hundreds of mW) Board size (configuration memory, external oscillator, sophisticated power management) Different power rails and power-up sequence Development speed (HDL languages, simulation, debugging) Radiation (cannot be fixed in SW) Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

14. Power consumption – SRAM FPGAs Duty cycling is not a perfect solution: high static power (disabling clocks is not enough) slow and high power reconfiguration memory is lost if static power is removed Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

15. STATIC and Dynamic Power • Static power • serious issue in FPGAs (~ x10 transistors needed) • increases as transistor sizeand Vth decreases • Dynamic (active) power • V2Cf • Can be controlled by the application developer • I/O switching • Clock scaling • Duty cycling • Lower device utilization Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

16. Low power Flash FPGAs • Very low static power (micro W range) • Somewhat lower dynamic power • Smaller board space (configuration) • Instantly “ON” • No configuration loading, no in-rush current • Radiation resistance • Duty cycling is a viable option for WSN application Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

17. Low Power Flash FPGAs Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

18. Actel IGLOO Device Family • Flash-based low-power FPGAs • FlashFreeze mode • Clock domains suspended, high-impedance I/O • Memory contents (FF, BRAM) preserved • Low cost (< $1), small size (3mm) • ARM Cortex M1 optional processor core (30-40% device utilization) • IGLOO, IGLOO nano, IGLOO plus (I/O optimized) • Sizes comparable to medium size low-end SRAM FPGAs Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

19. Low power design tricks • Decrease the average logic-switching activity • FSM encoding (one hot, Gray) • Glitch reduction or pushing it downstream • Reduce the amount of logic switching at each clock edge • Both rising and falling clock edges should be used • Reduce the propagation of the switching activity • Pipelines • Lower the capacitance of the routing network and clock spines • Use low voltage I/O standards Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

20. Drawbacks – lessons learned • Significantly slower maximum operating speed (10-40MHz) • Smaller gate count (130nm process node) • Flip-flops and comb. logic is a shared resource • effective device size is smaller than expected • No initialized memory • problematic with small processor cores • Limited number of reprogramming (1000) • Much longer (re)programming time • No hardware multipliers, DSP blocks (yet?) Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

21. Application in WSNs • (Flash-based) FPGAs are ready to be used in motes running on batteries • SRAM FPGAs: hundreds of mW • Flash FPGAs: tens of mWdynamic, uWstatic • Local signal processing, hard real-time services (eg.: timesync) • HDL-based design flow is a (the most serious? ) drawback • More advanced power rail requirements Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

22. Similar directions • Parallax Propeller chip • 8 32bit controllers (cogs) • Low pin count • SPIN programming language • Highly flexibleperipheral(Timer-based) Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

23. Similar Directions Cypress Semiconductor PSoC 8bit Harvard-architecture uC (M8C) Configurabledigital and analog blocks and interconnect Drives the iPod scroll-wheel (CapSense) Ideal for simple, small and low-power WSN applications Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS

24. THE END Low Power FPGAs in Wireless Sensor Networks Peter Volgyesi, Vanderbilt University, ISIS