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P rogrammable Logic Device Devices and Applications. T o p i c s. Architecture and Characteristic of PLD FPGA Devices Development Boards FPGA Design Flow Application in Signal Processing. Architecture of MAX 7000 MacroCell. Architecture of MAX 7000. Architecture of CycloneIII LE.
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Programmable Logic Device Devicesand Applications
T o p i c s • Architectureand Characteristic of PLD • FPGADevices • Development Boards • FPGADesign Flow • Application in Signal Processing
Global PLDProviders • www.altera.com • Inventor of CPLD,Best FPGA • www.xilinx.com • Inventor of FPGA,Best FPGA • www.latticesemi.com • Inventor of ISP • www.actel.com • For G.I. and Astrionics
CPLDs based on LUT General CPLDs 65nm、90nm、130nm Low Cost FPGAs 40nm、65nm、90nm、130nm High Performance FPGAs Low Cost FPGAs with High Speed transceiver structured ASICs Better Performance Lower Cost
Virtex Series High Performance FPGAs Vitrex-5 for latest Vitrex-5 TXT,120Gbps in a single chip! Spartan Series Low Cost FPGAs Spartan-3E for latest CoolRunner Series CPLDs CoolRunner-II for latest
Anti-fuse FPGAs( Radiation protection ,perfect in security ) • Flash Based FPGAs ( Inner configuration ,perfect in security ) • CPLDs (EEPROM) • FPGAs with ViaLink(Low power cost, perfect in security
Earliest access to 40-nm technology AND a low-risk path to production • Highest density, highest performance, AND lowest power
Stratix IV E FPGAs • Up to 680K high-performance logic elements(LEs) • DSP blocks—with a parallel architecture and up to 1,360 embedded 18x18 multipliers running at 550 MHz, Stratix IV FPGAs deliver up to 748 GMACSof DSP performance, a level unmatched by competing devices • TriMatrix memory—three memory block sizes with up to 22.4 Mbits of embedded memory running at 600 MHz • An FPGA fabric that is two speed grades , or 35 percent, faster than that of the nearest competitor
Transceiver-based Stratix IV GX FPGAs • Up to 48 high-speed transceivers supporting data rates of up to 8.5 Gbps, including hard intellectual property (IP) protocols and signal integrity optimization blocks • Up to four hard IP blocks for PCI Express (PCIe) compliant with PCIe Base Specification 2.0, 1.1, or 1.0, supporting x1, x2, x4, and x8 configurations. You’ll also have support for end-port and root-port applications. • LVDS support up to 1.6 Gbps • Up to four 72-bit high-speed DDR3 interfaces at 1,067 Mbps (533 MHz)
256-bit key AES encryption with FIPS-197 certification
to 120,000 logic elements (LEs) and4 Mbits embedded memory . • 260-MHz multiplier performance with the highest multiplier-to-logic ratio in the industry. • Robust clock management and synthesis with dynamically reconfigurable and flexible phase-locked loops (PLLs). • Improved signal integrity with adjustable I/O slew rates. • Support for high-speed external memory interfaces including DDR,DDR2, SDR SDRAM, and QDRII SRAM. • Support for I/O standards including LVTTL, LVCMOS, SSTL, HSTL, PCI Express, LVPECL, LVDS, mini-LVDS, RSDS, PPDS.
Xilinx XC3S500E FPGA • Xilinx XCF04 Platform Flash for storing FPGA configurations • St Microelectronics M25P16 16Mbit Serial Flash • Intel TE28F128 (or JS28F128) 128Mbit StrataFlash • Linear Technologies Power Supplies • Texas Instruments TPS75003 Triple-Supply Power Management IC • SMSC LAN83C185 Ethernet PHY • Micron 256Mbit DDR SDRAM