Easily Build Designs Using Altera’s Video and Image Processing Framework

1. Easily Build Designs Using Altera’s Video and Image Processing Framework 2010 Technology Roadshow

2. Agenda • What is the video framework?                 • Six steps to building a video system • Video design demo using SOPC Builder • Summary    

3. Altera Video Design Framework

4. Altera Video Design Framework IP Building Blocks Pre-Verified Video Reference Designs Video Kit Portfolio Building Blocks Video Streaming Interface Higher Designer Productivity = Faster Time to Market

5. Video IP Building Blocks: IPS-Video ‘Interlacer’ core in v10.1

6. Open, Low-Overhead, Interface Standard:Avalon Streaming (ST) Video Open Interface Protocol for Streaming Video Datapaths and Memory-Mapped Control Paths

7. Portfolio of Reference Designs

8. Video Development Kits Cyclone III FPGA, $1,895 Stratix IV FPGA, $4,995 Arria II GX FPGA, $2,995 Cyclone III FPGA, $2,995

9. Six Steps to Building a Video System

10. General Video System Design Flow Design Specification No OK? Yes Hardware Implementation Software Implementation for System Bring Up No OK? Yes Yes Software only change? Full Software Implementation No OK? Yes Project complete

11. Design Specification OK? No Yes Hardware Implementation Software Implementation for System Bring Up OK? No Yes Software only change? Yes Full Software Implementation OK? No Yes Project complete Implementation • Build system incrementally in six steps • Always follow the steps! 1. Implement top-level HDL 2. Implement video output 3. Add soft processor for control and debug Can be removed later if not required 4. Implement video input 5. Implement frame sync and memory interface 6. Integrate video processing functions

12. Hardware Implementation—Video Output Use a TPG Instead of Video Source to Test Video Output PLLs SDI-Tx SDI TX SDI-Rx SDI RX Clocked Video Output Test Pattern Generator VCXO DVI Tx DVI TX PFD DVI RX SOPC Builder Top level (HDL)

13. Hardware Implementation—Nios II Processor Add Nios II processor. Write Software for Control and Debug Add Board Peripherals PLLs SDI-Tx Nios II Processor Buttons JTAG UART LEDs SDI TX SDI-Rx SDI RX Clocked Video Output Test Pattern Generator VCXO DVI Tx DVI TX PFD DVI RX SOPC Builder Top level (HDL)

14. Hardware Implementation—Video Input Add Video Input (no datapath yet) PLLs SDI-Tx Nios II Processor Buttons JTAG UART LEDs SDI Tx SDI-Rx SDI Rx Clocked Video Output Test Pattern Generator Clocked Video Input Terminator VCXO DVI Tx DVI Tx PFD DVI Rx SOPC Builder Top level (HDL)

15. Hardware Implementation – Memory Controller Add Frame Buffer and Memory Controller PLLs SDI-Tx Nios II Buttons JTAG UART LEDs SDI Tx SDI-Rx SDI Rx Clocked Video Output Clocked Video Input Test Pattern Generator Frame Buffer Terminator VCXO DVI Tx DVI Tx PFD SOPC Builder DVI Rx DDRX Memory Controller Top level (HDL)

16. Hardware Implementation – Video Processing Add Video Processing Functions PLLs SDI-Tx Nios II Buttons JTAG UART LEDs SDI Tx SDI-Rx SDI Rx Clocked Video Output Clocked Video Input Frame Buffer Scaler Chroma Resampler Deinterlacer CSC VCXO DVI Tx DVI Tx PFD SOPC Builder DVI Rx DDRX Memory Controller Top level (HDL)

17. Video Design Demo Using SOPC Builder

18. Summary • Altera video design framework enables rapid development • Mix and match existing IP—leverage Altera’s open interface standard • Automatically integrate embedded processors and arbitration logic • Leverage building block IP provided by Altera • Use existing reference designs as starting points • Rapid prototyping • Implement design using the appropriate development boards • Test the design with actual video signals

19. Thank You!For more information visit: www.altera.com