Power-aware Design - Part I Energy Consumers & Sources

1. Power-aware Design - Part IEnergy Consumers & Sources EE202A (Fall 2004): Lecture #8

2. Reading List for This Lecture • Required • D. Rakhmatov, S. Vrudhula, and D. Wallach, “A model for battery lifetime analysis for organizing applications on a pocket computer”, IEEE Transactions on VLSI, to appear.http://nesl.ee.ucla.edu/pw/ee202a/rakhmatov-tvlsi-2003.pdf • Thomas Martin and Daniel Seiwiorek, "Non-Ideal Battery Behavior and Its Impact on Power Performance Trade-offs in Wearable Computing," Proceedings of the 1999 International Symposium on Wearable Computers, San Francisco, CA, October 18-19, 1999; pp. 101-106. http://www.ece.vt.edu/~tlmartin/papers/nonideal_formatted.pdf • Recommended • V. Raghunathan, C. Schurgers, S. Park, and M. Srivastava, "Energy-aware Wireless Microsensor Networks," IEEE Signal Processing Magazine, March 2002. p. 40-50. • Others • None

3. Why worry about power?Intel vs. Duracell 16x • No Moore’s Law in batteries: 2-3%/year growth 14x Processor (MIPS) 12x Hard Disk (capacity) 10x Improvement(compared to year 0) 8x Memory (capacity) 6x 4x Battery (energy stored) 2x 1x 0 1 2 3 4 5 6 Time (years)

4. Current Battery Technology is Inadequate • Example: 20-watt battery • NiCd weighs 0.5 kg, lasts 1 hr, and costs $20 • Comparable Li-Ion lasts 3 hrs, but costs > 4x more

5. The Showstopper: Energy • Need long lifetime with battery operation • No infrastructure, high deployment & replenishment costs • Continual improvement in functionality, size, weight, and power • 1.6x/year in DSP power • sensing and RF components based on MEMs • But • energy to wirelessly transport bits is ~constant • Shannon, Maxwell • fundamental limit on ADC speed*resolution/power • no Moore’s law for battery technology • ~ 5%/year The Future Single-chip Wireless Sensor Node

6. Comparison of Energy Sources Assume 1mW Average as definition of “Scavenged Energy”

7. Will IC technology alone help? • Speed power efficiency has indeed gone up • 10x / 2.5 years for Ps and DSPs in 1990s • degraded before 90s • > 100 mW/MIP to < 1 mW/MIP since 1990 • IC processes have provided 10x / 8 years since 1965 • rest from power conscious IC design in recent years • Lower power for a given function & performance • e.g. 1.6x / year reduction since early 80s for DSPs (source TI)

8. But … • Help from IC technology will slow down • e.g. circuit voltage reduction have provided big gains • used to be 5V, now around 1.5-2V • expected to plateau • Big gains from low-power IC design tricks behind us • Strong indications of continued exponential increase in operating frequency and # of functions • we all want color displays, multimedia, wireless comm., speech recognition on our PDAs! • increase of 10x / 7 yrs in gates, 10x/9 yrs in frequency • Power requirements of wireless communication functions also constrained by Shannon & Maxwell!

9. IC Technology Trends and Power[source: De99 from Intel] • Transistor scaling • Each generation of technology scaling results in 30% reduction in minimum feature size • now mostly “constant electric field” scaling • gate length, effective electrical gate oxide thickness, and supply voltage scaled by 30% • use to be constant voltage scaling previously • Worst-case sub-threshold leakage current approx. constant • but, have been able to maintain approximately constant drive current per unit width of transistor, at reduced supply voltage • Net result: • gate delay reduced by 30% • areal component of junction capacitances reduced by 30% • transistor density is doubled (I.e. die area reduced by 50%) • total capacitance on chip reduced by 30% • transistor capacitance per unit area increases by 43%

10. IC Technology Trends and Power(contd.) • Power • constant electric field scaling: • 43% higher f, 30% less C, 30% less V • energy per clock cycle reduces by 65% • assumes unchanged ave. # of switching transitions per cycle • power reduces by 50% • If can’t scale Vdd and Vt (e.g. if electric field < max for reliability) • energy reduce by 30% • power remains constant • can’t add more transistors without increasing power budget! • constant voltage scaling was employed until 0.8 micron • But, max power depends not only on technology, but also on implementation (size, frequency, circuit style, microarchitecture etc.) • Metric: “active” or “switched” capacitance (P/V2f) per unit area • scaling theory predicts 43% increase • real life: 30-35% (logic transistor density improvement < x2)

11. IC Technology Trends and Power (contd.) • Clock frequency • doubles every technology generation • instead of 43% (as predicted by 30% gate delay improvement) • why? • ave # of gate delays in a clock cycle is reducing (more pipelined) • advanced circuit techniques • Die size • size of die increases 25% per technology generation • new designs add more transistors (integration, complexity) • Interconnect scaling • thinner, tighter  higher resistance and capacitance • more layers • interconnect distribution (# of wires vs. length) does not change significantly

12. Nuclear Reactor Hot plate Projections about Power • Power dissipation of microprocessors • from 100W to 2,000W if supply voltage is scaled • supply current from 100A to 3000A • 10,000W if supply voltage not scaled • Die size will have to be restricted • 15 mm die will mean power will stay around 100W and supply current around 300A • 22 mm die will have 200W and 500A • Leakage power ignored – but increasingly important • A key problem: technology scaling still being done with delay as the primary goal (30% reduction) as opposed to a goal that incorporates power as well (e.g. Energy-Delay) Source: Intel/[Flautner01]

13. Barriers to Future Voltage Scaling • Voltage scaling requires threshold voltage Vt to be scaled as well (15% per generation) • this increases sub-threshold leakage current • impact on power consumption and circuit robustness • Leakage power • total leakage current goes up 7.5x per generation • leakage power power by 5x • soon will become a significant portion of total • active power remains constant for constant die size • leakage power, and therefore total power, can be substantially reduced by cooling • Essential to control die temperature • power density (W/cm2): 0.6 micron chips surpassed a hot plate!

14. Barriers to Future Voltage Scaling (contd.) • Circuit performance and robustness • scaling V and Vt poses serious challenges to special circuits such as domino logic, sense amplifiers • increase in sub-threshold leakage current impacts bit line delay on large on-chip caches • divergence of logic and cache performance • Single event upsets: soft errors • caused by alpha particles in material and cosmic rays • reduced capacitance  lower energy to flip a bit • soft error rate will increase • adding more capacitance undesirable • memory is typically ECC protected, but not latches, flip-flops etc.

15. Trends in Total Power Consumption source : arpa-esto DEC 21164 • Frightening: proportional to area & frequency microprocessor power dissipation

16. System Design for Low Power • Need to explicitly design the system with power consumption or energy efficiency in mind • Fortunately, IC technology still continue to help indirectly by increasing level of integration • more and faster transistors can enable low-power system architectures and design techniques • e.g. system integration on a chip can reduce the significant circuit I/O power consumption • Energy efficient design of higher layers of the system also help • energy efficient protocols, power-aware apps. etc.

17. System Design for Low Power (contd.) • Energy efficiency cuts across all system layers • entire network, not just the node • everything: circuit, logic, software, protocols, algorithms, user interface, power supply... • complex global optimization problem • Need to choose the right metric • e.g. individual node vs. network lifetime • Trade-off between energy consumption & QoS • optimize energy metric while meeting QoS constraint • Power-awareness, and not just low power • right energy at the right time and place

18. Sources of Power Consumption

19. Processing Programmable Ps & DSPs (apps, protocols etc.) ASICs Memory Communication RF Transceiver Radio Modem Where does the Power Go? Peripherals Disk Display Power Supply DC-DC Converter Battery

20. Power Consumption for a Computer with Wireless NIC

21. Energy Consumption ofWireless NICs (Wavelan)

22. Power Consumption in Post-PC Devices • Pocket computers, PDAs, wireless pads, wireless sensors, pagers, cell phones • Energy and power usage of these devices is markedly different from laptop and notebook computers • much wider dynamic range of power demand • share of memory, communication and signal processing subsystems become more important • disk storage and displays disappear or become simpler • Design of power-aware higher layer applications and protocols need to be re-evaluated

23. Example: Power Consumption for Berkeley’s InfoPad Terminal Without Optional Video Display Total = 6.8W (with processor at 7% duty cycle) With Optional Video Display Total = 9.6W (with processor at 7% duty cycle)

24. Example: Power Consumption for Compaq WRL’s Itsy Computer • System power < 1W • doing nothing (processor 95% idle) • 107 mW @ 206 MHz • 77 mW @ 59 MHz • 62 mW @ 59 MHz, low voltage • MPEG-1 with audio • 850 mW @ 206 MHz (16% idle) • Dictation • 775 mW @ 206 MHz (< 0.5% idle) • text-to-speech • 420 mW @ 206 MHz (53% idle) • 365 mW @ 74 MHz, low voltage ( < 0.5% idle) • Processor: 200 mW • 42-50% of typical total • LCD: 30-38 mW • 15% of typical total • 30-40% in notebooks Itsy v1 StrongARM 1100 59–206 MHz (300 us to switch) 2 core voltages (1.5V, 1.23V) 64M DRAM / 32M FLASH Touchscreen & 320x200 LCD codec, microphone & speaker serial, IrDA

25. Example: Power Consumption for Compaq’s iPAQ 206MHz StrongArm SA-1110 processor 320x240 resolution color TFT LCD Touch screen 32MB SDRAM / 16MB Flash memory USB/RS-232/IrDA connection Speaker/Microphone Lithium Polymer battery PCMCIA card expansion pack & CF card expansion pack • * Note • CPU is idle state of most of its time • Audio, IrDA, RS232 power is measured when each part is idling • Etc includes CPU, flash memory, touch screen and all other devices • Frontlight brightness was 16

26. The Power Hogs in Post-PC Devices • Wireless modem • Rx is comparable, and may be more, than Tx • DC-DC conversion • Displays • Handheld flat panel display 6.4W • Helmet mounted display 4.9W • Integrated sight module display 2.6W • Digital subsystem for protocol & applications • note: in InfoPad, the processor is used primarily for simple management of transmit modem schedule • Storage peripherals

27. Energy Consumption in Wireless Sensor Nodes • Processing • excluding low-level processing for radio, sensors, actuators • Radio • Sensors • Actuators • Power supply

28. Example: Sensor Nodes • High-end sensor node: Rockwell WINS nodes • StrongARM 1100 processor • Connexant’s RDSSS9M 900MHz DECT radio(100 kbps, ~ 100m) • Seismic sensor • Low-end sensor node: Berkeley’s COTS motes • Atmel AS90LS8535 microcontroller • RF Monolithic’s DR3000 radio (2.4, 19.2, 115 kbps, ~ 10-30m) light, temperature, 10 kbps @ 20m

29. Processing • Common sensor node processors: • Atmel AVR, Intel 8051, StrongARM, XScale, ARM Thumb, SH Risc • Power consumption all over the map, e.g. • 16.5 mW for ATMega128L @ 4MHz • 75 mW for ARM Thumb @ 40 MHz • But, don’t confuse low-power and energy-efficiency! • Example • 242 MIPS/W for ATMega128L @ 4MHz (4nJ/Instruction) • 480 MIPS/W for ARM Thumb @ 40 MHz (2.1 nJ/Instruction) • Other examples: • 0.2 nJ/Instruction for Cygnal C8051F300 @ 32KHz, 3.3V • 0.35 nJ/Instruction for IBM 405LP @ 152 MHz, 1.0V • 0.5 nJ/Instruction for Cygnal C8051F300 @ 25MHz, 3.3V • 0.8 nJ/Instruction for TMS320VC5510 @ 200 MHz, 1.5V • 1.1 nJ/Instruction for Xscale PXA250 @ 400 MHz, 1.3V • 1.3 nJ/Instruction for IBM 405LP @ 380 MHz, 1.8V • 1.9 nJ/Instruction for Xscale PXA250 @ 130 MHz, .85V (leakage!) • And, the above don’t even factor in operand size differences! • However, need power management to actually exploit energy efficiency • Idle and sleep modes, variable voltage and frequency

30. Radio • Energy per bit in radios is a strong function of desired communication performance and choice of modulation • Range and BER for given channel condition (noise, multipath and Doppler fading) • Watch out: different people count energy differently • E.g. • Mote’s RFM radio is only a transceiver, and a lot of low-level processing takes place in the main CPU • While, typical 802.11b radios do everything up to MAC and link level encryption in the “radio” • Transmit, receive, idle, and sleep modes • Variable modulation, coding • Currently around 150 nJ/bit for short rangeS

31. Radio Power Consumption Tx: Sender Rx: Receiver Incoming information Outgoing information Channel Power amplifier Transmit electronics Receive electronics nJ/bit nJ/bit nJ/bit ~ 50 m (WLAN) ~ 10 m (Mote) ~ 1 km (GSM)

32. Dominance of Electronics at Short Ranges Sender Side Power Consumption d Static Power,Digital Processing Power amp,Receiver Sensitivity Re: Min et. al., Mobicom 2002 (Poster)

33. Radio Electronics Trends Radiated power 63 mW (18 dBm) Intersil PRISM II (Nokia C021 wireless LAN) Power amplifier 600 mW (~11% efficiency) Analog electronics 240 mW Digital electronics 170 mW • Trends: • Move functionality from the analog to the digital electronics • Digital electronics benefit most from technology improvements • Analog a bottleneck • Digital complexity still increasing (robustness)

34. Computation & Communication Mote-class Node • Energy/bit  Energy/op large even for short ranges! WINS-class Node Energy breakdown for image Energy breakdown for acoustic Decode Decode Transmit Encode Encode Receive Receive Transmit

35. Sensing • Several energy consumption sources • transducer • front-end processing and signal conditioning • analog, digital • ADC conversion • Major source of power consumption • Function of speed and resolution • Fundamental limit on (speed*resolution/power) metric • Important to select ADC for resolution that is truly required • Diversity of sensors: no general conclusions can be drawn • Low-power modalities • Temperature, light, accelerometer • Medium-power modalities • Acoustic, magnetic • High-power modalities • Image, video, beamforming

36. Actuation • Emerging sensor platforms • Mounted on mobile robots • Antennas or sensors that can be actuated • Energy trade-offs not yet studied • Some thoughts: • Actuation often done with fuel, which has much higher energy density than batteries • E.g. anecdotal evidence that in some UAVs the flight time is longer than the up time of the wireless camera mounted on it • Actuation done during boot-up or once in a while may have significant payoffs • E.g. mechanically repositioning the antenna once may be better than paying higher communication energy cost for all subsequent packets • E.g. moving a few nodes may result in a more uniform distribution of node, and thus longer system lifetime

37. Power Analysis of RSC’s WINS Nodes Summary • Processor • Active = 360 mW • doing repeated transmit/receive • Sleep = 41 mW • Off = 0.9 mW • Sensor = 23 mW • Processor : Tx = 1 : 2 • Processor : Rx = 1 : 1 • Total Tx : Rx = 4 : 3 at maximum range • comparable at lower Tx

38. Power Analysis of Mote-like Node

39. Some Observations • Using low-power components and trading-off unnecessary performance for power savings can have orders of magnitude impact • Node power consumption is strongly dependent on the operating mode • E.g. WINS consumes only 1/6-th the power when MCU is asleep as opposed to active • At short ranges, the Rx power consumption > T power consumption • multihop relaying not necessarily desirable • Idle radio consumes almost as much power as radio in Rx mode • Radio needs to be completely shut off to save power as in sensor networks idle time dominates • MAC protocols that do not “listen” a lot • Processor power fairly significant (30-50%) share of overall power • In WINS node, radio consumes 33 mW in “sleep” vs. “removed” • Argues for module level power shutdown • Sensor transducer power negligible • Use sensors to provide wakeup signal for processor and radio • Not true for active sensors though…

40. Metrics for Power • Power • sets battery life in hours • problem: power  frequency (slow the system!) • Energy per operation • fixes obvious problem with the power metric • but can cheat by doing stuff that will slow the chip • Energy/op = Power * Delay/op • Metric should capture both energy and performance: e.g. Energy/Op * Delay/Op • Energy*Delay = Power*(Delay/Op)2

41. Communication vs. Computing • A good measure is J/bit vs. J/ instruction • Examples • Rockwell WINS nodes: 1500 to 2700 • Medusa (similar to UCB’s motes): 220 to 2900 • Sensoria’s WINS NG 2.0 nodes: ~ 1400 • But watch out: • not all instructions are the same: 8-bit vs. 32-bit • not all bits are the same: distance, error probability

42. Sources of Power: Batteries

43. Battery Characteristics • Important characteristics: • energy density (Wh/liter) and specific energy (Wh/kg) • power density (W/liter) and specific power (W/kg) • open-circuit voltage, operating voltage • cut-off voltage (at which considered discharged) • shelf life (leakage) • cycle life • The above are decided by “system chemistry” • advances in materials and packaging have resulted in significant changes in older systems • carbon-zinc, alkaline manganese, NiCd, lead-acid • new systems • primary and secondary (rechargeable) Li • secondary zinc-air, Ni-metal hydride

44. Modeling the Battery Behavior • Theoretical capacity of battery is decided by the amount of the active material in the cell • batteries often modeled as buckets of constant energy • e.g. halving the power by halving the clock frequency is assumed to double the computation time while maintaining constant computation per battery life • In reality, delivered or nominal capacity depends on how the battery is discharged • discharge rate (load current) • discharge profile and duty cycle • operating voltage and power level drained

45. Battery Capacity from [Powers95] • Current in “C” rating: load current nomralized to battery’s capacity • e.g. a discharge current of 1C for a capacity of 500 mA-hrs is 500 mA

46. Battery Capacity vs. Discharge Current • Amount of energy delivered is decreased as the current (rate at which power is drawn) is increased • rated as ampere hours or watt hours when discharged at a specific rate to a specific cut-off voltage • primary cells rated at a current which is 1/100th of the capacity in ampere hours (C/100) • secondary cells are rated at C/20 or C/10 • At high currents, the diffusion process that moves new active material from electrolytes to the electrode cannot keep up • concentration of active material at cathode drops to zero, and cell voltage goes down below cut-off • even though active material in cell is not exhausted!

47. Battery Capacity vs. Discharge Current: Peukert’s Formula • Energy capacity: C = k/I • k = constant dependent on chemistry & design •  = 0 for ideal battery (constant capacity), up to 0.7 for most loads in real batteries • also depends on chemistry and design • Good first order approximation • does not capture effects of discharge profile • Battery life at constant voltage and current L = C/P = C/(V.I) = (k/V).I-(1+)

48. Ragone Plots (log-log plot) Specific Power W/kg Specific Energy Wh/kg

49. Amount of Computation during Battery Lifetime • Consider a system modification that changes performance by factor n and power by factor x • total work (= speed x lifetime) will change by n.x -(1+) • e.g. reducing the clock frequency by xN reduces power by xN (N>1) & reduces performance by xN, • work done changes by (1/N)x(1/N) -(1+) = N • > 1 for >0 • however, can’t just go on reducing frequency • static power dissipated even at zero frequency • P = V.I = V.(S+Df) •  optimum frequency to maximize computation • problem: system performance does not change linearly with frequency (e.g. memory bottlenecks)

50. Alternate Equivalent View of the Battery • Manufacturer’s often give battery efficiency (%) vs. discharge rate (or discharge current ratio) • discharge rate = Iave/Irated • Battery cannot respond to instantaneous changes in current • so, a time constant t used to calculate Iave • Given actual energy drawn by the circuit, one can use the battery efficiency to calculate the actual depletion in the stored energy in the battery • Example: battery efficiency is 60% and its rated capacity is 100 mAh @ 1V • computed average DC-DC current of 300 mA would drain the battery in 12 min, while at 100% efficiency it would last 1 hr