EE 201C Modeling of VLSI Circuits and Systems TR 12-2pm

1. EE 201CModeling of VLSI Circuits and SystemsTR 12-2pm Instructor: Lei He Email: LHE@ee.ucla.edu

2. Instructor Info • Email: LHE@ee.ucla.edu • Phone: 310-206-2037 • Office: Boelter Hall 6731D • Office hours: • Tus 2-3pm • Thur 4-5pm • or by appointment for Wed. • The best way to reach me: • Email with EE201 in subject line

3. Who should and can take this course • Those want to learn timing, signal and power integrity, stochastic power/thermal for both SoC and SiP • Mainly from the angel of designers • Background required • Basics of IC • Matlab and SPICE (both could be learned in this class)

4. VLSI Design and Verification Cycle System Specification Functional Design and Verification X=(AB*CD)+(A+D)+(A(B+C)) Y=(A(B+C))+AC+D+A(BC+D)) Logic Design and Verification Circuit Design and Verification • Verification techniques • Formal verification • Logic/circuit simulation • Functional and logic emulation

5. VLSI Design and Verification Cycle (cont.) Physical Design and Verification Fabrication and Testing Packaging • Layout verification • LVS, DRC, ERC • Timing, SI, PI, DFM (applied to circuit design as well) • Modeling and simulation is the core component for design and verification considering timing/SI/PI/DFM

6. 201C Course Outline and Schedule Interconnect and timing modeling (3 weeks) Parasitic (RLC and thermal RC) extraction Delay modeling and model order reduction 2 hws (e.g., model order reduction in Matlab) On-chip timing and integrity (4 weeks) Static timing and noise analysis for logic and on-chip interconnects Process variation, stochastic timing, power and noise analysis Stochastic power and thermal integrity 3 hws (e.g., SPICE-based stochastic modeling of SRAM cells) Beyond-die signal and power integrity (3 weeks) Chip-package co-design with signal and power integrity Noise analysis for high-speed signaling and other analog components 2 hws (e.g., Matlab-based decap determination and equalizer design) Final project: SPICE-based stochastic design of SRAM arrays

7. Examples of hws Example 1: Matlab coding of PRIMA Extend single-point model order reduction to multi-point MOR Majority of program is given Example 2: SPICE-based stochastic modeling of SRAM cells Consider spatially-correlated Leff variation and random Vt variation, and take into account dependence between Leff and Vt Reduce the number of SPICE runs for required accuracy Monte Carlo vs Pesudo Monte Carlo vs non Monte Carlo Example 3: off-chip signal and power integrity Matlab based design ISI (inter symbol interference) reduction for transmission line Power noise reduction via off-chip decap

8. Final Project Design of SRAM Array considering PVT variations Could be a single student or a team of two students Decide the architecture and SPICE netlist Validate via stochastic SPICE simulation Develop a report up to 12 page report using ACM style http://www.acm.org/sigs/pubs/proceed/template.htm Deliver a 20 minute presentation during the finals week, like a conference talk (audio or video for online program) Reports, references, and audio/video uploaded to class wiki

9. Grading Policy • 7 Homework 70 • each hw 8 pts for correctness, 2pts for optimality • Final project 30 20 pts for meeting design spec 10 pts for novelty, and quality of report and presentation • A  score > 85

10. References for this Course Web sites • http://eda.ee.ucla.edu/EE201C (wiki website) • ID: spring2010 • password BH5273 • http://eda.ee.ucla.edu/EE201A-04Spring/index.html Selected papers from leading journals and conferences Tan and He, “Advanced Model Order Reduction Techniques for VLSI Designs”, Cambridge University Press, 2006 H. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison Wesley