The M68000 Processor

1. The M68000 Processor ECE511: Digital System & Microprocessor

2. What we are going to learn in this session: • M68k hardware architecture: • M68k pin assignments • Pin functions.

3. The M68k Microprocessor • M68000, M68k microprocessor. • Motorola Semiconductors, 1979. • 16-bit processor, but can perform 32-bit operations. • Speed: 8-12 MHz.

4. The M68k Microprocessor • Very advanced compared to 8-bit processors: • 16-bit data bus, 24-bit address bus. • Can execute instructions twice as fast. • Still available today: • Simple, practical commands. • Robust: can be used for many applications.

5. The M68k Microprocessor

6. The M68k Microprocessor • Has 64 pins: • Power supply and clock (5 pins). • Processor status (3 pins). • 6800 peripheral control (3 pins). • System control (3 pins). • Data bus (16 pins). • Address bus (23 + 1 pins). • Asynchronous bus control (5 pins). • Bus arbitration control (3 pins). • Interrupt control (3 pins).

7. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 M68k Pin-Out *A0 is used inside 68k

8. Power Supply & Clock

9. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

10. Vcc & GND • Vcc: • Voltage supply. • Gives electrical power to 68k. • 2 pins into M68k. • supplies 5V (±5%) voltage. • Connected to power supply. • GND: • Ground connection. • Lower potential for current flow. • 2 pins out of M68k.

11. CLK • Clock signal. • 1 pin from timing circuit. • Used for timing of: • Circuits connected to M68k. • Synchronous data transfer. • Asynchronous data transfer (less important). • 50% duty cycle: • 50% up, 50% down. • Fall-To-Rise, Rise-To-Fall = 10ns. • Slower devices use modified signal from CLK.

12. 10 ns 10 ns CLK Signal CLK 50% up 50% down

13. Processor Status Pins

14. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

15. FC0, FC1, FC2 • Function Code pins. • 3 pins output. • Indicates type of cycle currently executing: • Operation on user program/data. • Operation on supervisor program/data. • Interrupt acknowledge. • Values assigned by M68k. • AS must be low for valid output.

16. FC2 FC1 FC0 What the 68k is doing 0 0 0 0 Reserved (No meaning) 0 0 0 1 Accessing User Data 0 0 1 0 Accessing User Program 0 0 1 1 Reserved (No meaning) 0 1 0 0 Reserved (No meaning) 0 1 0 1 Accessing Supervisor Data 0 1 1 0 Accessing Supervisor Program 0 1 1 1 Acknowledging Interrupt Request 1 X X X Outputs not valid (AS is high). AS Function Code Description

17. Data Bus Address Bus FC to Protect Supervisor Memory

18. 68000 Device Requesting Interrupt FC0 INTACK FC1 FC2 AS FC to Generate Interrupt Acknowledge Signal

19. 6800 Peripheral Control

20. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

21. 6800 Peripheral Control • Allows M68k to interface with devices using older processors (M6800). • “Backward-Compatible.” • Three pins: • E: Clock • VMA: Valid Memory Address. • VPA: Valid Peripheral Address.

22. Synchronous Data Exchange • Mode where: • Data exchange performed using same timing. • Timing generated by single clock signal. • Shared by all synchronous devices.

23. E – 6800 Timing Signal • Synchronizes data transfer – M68k & 6800: • Shared timing signal for slower 6800 devices. • Generated by M68k (output). • Modified CLK signal (/10). • 40% duty cycle. • 40% up, 60% down.

24. CLK E 4 CLK cycles 6 CLK cycles Timing Signals: E vs. CLK After modified by M68k *Therefore, E has 40% duty cycle

25. VPA – Valid Peripheral Address • VPA – Valid Peripheral Address. • Input pin: received from 6800 device. • Functions: • Generates confirmation response to M68k. • Tells M68k that device exists and ready. • To tell M68k to synchronize to E.

26. VMA – Valid Memory Address • VMA – Valid Memory Address. • Output pin: sent by M68k to 6800 device. • Functions: • Informs the device that M68k is ready for data transfer. • To tell 6800 device that M68k is sync. with E.

27. M68k accesses device by referring to device’s memory address. Device detects attempt, responds by setting VPA to low. After receiving VPA, M68k knows that it has addressed a valid device. 1 2 3 How M68k Accesses 6800 Devices M68k 6800 Device

28. M68k 6800 Device M68k stops synchronizing with CLK, and starts synchronizing with E. Device receives VMA, knows M68k is ready. M68k activates VMA to inform device that it has synchronized with E. 4 6 5 7 Both parties begin data transfer. How M68k Accesses 6800 Devices

29. How 6800 Peripheral Control Works • M68k outputs device address on Address Bus. • M68k pulls AS low. • Two possible outcomes: • If device doesn’t exist, M68k begins exception processing. • If device exists, device responds using VPA. • M68k receives signal: • Sync. with E • Pulls VMA low – ready to begin transfer. • Data transfer begins.

30. System Control

31. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

32. System Control • Responsible for control during catastrophic system faults. • Consists of three pins (1 input, 2 bi-directional): • RESET: Reset pin. • HALT: Halt pin. • BERR: Bus error pin. • Functions: • To receive error notifications. • Stop/reset M68k operations. • Stop/reset peripherals.

33. BERR – Bus Error • Receives information of bus error. • From watchdog circuit. • Only informs M68k, doesn’t do anything else. • One-directional: into M68k. • Possible causes: • Invalid memory address. • Physical damage to bus. • Peripheral error.

34. HALT – Halt Signal • Causes M68k to pause from executing instructions. • If active: • M68k stops execution after current cycle. • Waits until HALT is inactive. • Resumes execution. • Is bi-directional: • From external circuit / M68k (STOP command). • Both have same effect. • Also used to restart M68k (together with RESET).

35. RESET – Reset Signal • Resets M68k / external circuit. • Is bi-directional: • If signal from external circuit, resets M68k (together with HALT for 10 clock cycles). • If signal from M68k, resets external circuitry connected to RESET pin (RESET instruction).

36. Watchdog Circuit M68k M68k executes current processing cycle. Watchdog detects problems during execution, tells M68k by activating BERR. M68k receives BERR signal, knows something is wrong. 1 2 3 4 M68k checks the status of HALT. How M68k Manages Bus Errors

37. M68k 5 If HALT is active. 5 If HALT is inactive. Start exception processing Re-run current processing cycle 6 Cancel the problem bus cycle, store all address, data, & control. 6 Cancel the problem bus cycle. 7 Set address & data bus to high impedance state. 7 Start bus exception processing. 8 Wait until HALT is inactive. 9 Load previous address, data & control codes, re-run execution of problem cycle.

38. Interrupt Control

39. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

40. Interrupt Control • Interrupt pins for M68k. • 3 pins (input). • Functions: • Used by external circuit to request interrupt. • Used to prioritize M68k tasks. • Generated by external circuits: • Important tasks assigned higher interrupts. • 7 levels: 0 (lowest) to 7 (highest).

41. IPL2 IPL1 IPL0 Interrupt level 1 1 1 0 (No Interrupt) 1 1 0 1 1 0 1 2 1 0 0 3 0 1 1 4 0 1 0 5 0 0 1 6 0 0 0 7 (Highest, Non-maskable ) Interrupt Control

42. External Peripheral M68k T S I2 I1 I0 X N Z V C Interrupt Example M68k is executing instructions normally. 1 2 External peripheral has important task for M68k. 3 External peripheral asks for attention by outputting interrupt on IPL0, IPL1, IPL2. M68k compares interrupt level to SR. 4

43. M68k 5 If external interrupt higher than current. 5 If external interrupt lower than current. 6 Wait for higher-level interrupt being handled. 6 Update interrupt bits, save controls, registers into stack. 7 Handle interrupt, restore interrupt bits. 8 Restore controls, registers, resume normal execution.

44. Bus Arbitration Control

45. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 *A0 is used inside 68k

46. Bus Arbitration Control • Carries signals that allow bus takeovers: • M68k releases bus control to external device. • Faster data transfer, multi-CPU architecture, less overhead. • M68k waits, then takes back bus control. • Lets external devices become bus masters: • Device must have own microcontroller. • Accesses other peripherals as if it was CPU. • Usually for DMA.

47. Example: Transferring Data from HDD (CPU as Bus Master) HDD Serial I/O Interrupt Circuit System Bus Memory CPU Timing All components must go through CPU for to transfer data.

48. Example: Transferring Data from HDD (HDD µC as Bus Master) HDD Micro- Controller Serial I/O Interrupt Circuit System Bus Memory CPU Timing Less CPU overhead, CPU can process instructions that don’t require bus.

49. BR – Bus Request • Used by external circuit to request bus control. • Input to M68k, 1 pin. • Connected to Bus Request output on Alternate Bus Master (ABM). • Sends and waits for M68k response.

50. BG – Bus Grant • Used by M68k to: • Acknowledge bus request. • Tell device that it will release bus control. • Output from M68k, 1 pin. • Connected to Bus Grant input on ABM. • Sends and waits for ABM response.