Computer Architecture I: Digital Design Dr. Robert D. Kent

1. Computer Architecture I: Digital Design Dr. Robert D. Kent CPU Registers Register Transfer and Microoperations

2. Review • We have introduced registers previously. • Registers are constructed using flip-flops and combinational circuits that enable one to: • Refresh volatile data • Load (Store) data • Clear storages (change all bits to 0) • Increment (and decrement) storages binarily • Complement storages • Select individual storage bits

3. Considering the next problem in design • When designing complex computer systems it is important to understand that we start from very small components for which the operational characteristics are extremely well defined. • We then applied Bottom-Up Hierarchical design to identify commonly used networks (ie. circuits) of smaller components, from SSI to MSI. At this stage the descriptive language (and symbols) changes. • SSI: + as OR transforms to MSI: + as ADD • Now as we consider MSI to LSI, and also MSI-to-MSI networks, such as the CPU, our language must again change to fit the nature of design.

4. Goals • The Mano model of the CPU Registers • Registers • Bus network • Register and Memory Transfer • A language for describing hardware function • A language for denoting implementation • A language that bridges LSI/MSI • Microoperations: Application examples • Arithmetic • Logic • Shift

5. The Mano model of the CPU Registers • CPU registers used in the textbook (Mano): • PC :: Program counter • IR :: Instruction register • AR :: Address register • DR :: Data register (also called MBR – Memory Buffer Reg.) • AC :: Accumulator • INR :: Input buffer register • OUTR :: Output buffer register • SCR :: Sequence counter register

6. The Mano model of the CPU Registers 1x8 MUX 8x1 MUX Data IN S S S 2 1 0 S S S 2 1 0 Register Address • CPU registers are organized on an internal bus network • Accessible using a multiplexer • Registers are selected according to selection inputs 0 1 2 3 4 5 6 7 PC Typically, the number of registers is chosen as a power of 2. This simplifies the choice of MUX and the bus architecture. AR DR IR Data OUT AC INR OUTR Demultiplexers are used to input data to registers. SCR Register Address

7. Reminder! • CPU register operations should be among the fastest of hardware operations • All instructions are executed in CPU • Few registers implies more complex circuits may be employed to control data processing and workflow • We need a language that allows us to describe what we want to happen (operationally) in a circuit, while achieving an actual working hardware system to accomplish our requirements • We must also understand the complexities or behaviours of the circuits, such as performance based on numbers of logic stages, degrees of parallel versus serial capacity, response and other factors

8. Register Transfer • First, review what we have learned so far about registers • We combined the basic building blocks of bit storage units (ie. flip-flops) to form storage units of multiple bits called registers • We combined registers with more complicated circuitry to perform various operations • Some serial operations • Some parallel operations • We combined several operations together into even more complicated circuits • The choice of operation is determined by Selector inputs using either Multi-Input Control, or Multiplexer Selection.

9. Register – Parallel Load Load I0 I1 Clk D Q C D Q C P0 P1 • Register flip-flops should refresh or load simultaneously. Single Operation

10. Register – Count/Load/Clear J Q C K J Q C K • Combine counting (INC), loading (L) and synchronous clearing (C). Can also add Complementation (J=K=1). C L Inc I0 I1 Clk Multi-Input Selection: Multiple Operations A0 A1 Carry Out (See Fig. 2-11 in Mano)

11. Register – Shift/Load/Refresh • Bi-directional shifting can be combined with parallel load and refresh operations. This requires use of multiplexers.

12. Register – Shift/Load/Refresh D Q C D Q C • Bi-directional shifting can be combined with parallel load and refresh operations. Multiplexer Selection: Multiple Operations S0 S1 Serial in I0 Serial in I1 Clk S0 S1 0 4x1 1 MUX 2 3 A0 A1 S0 S1 0 4x1 1 MUX 2 3 (See Fig. 2-9 in Mano)

13. Registers: Multi-Operation Control • Selection of specific operations (or even groups of operations) can be accomplished in several ways. • Single selection • Dedicated circuits • Multi-selection • Multiplexed selection • Multi-input selection • Hybrid selection, combining both multiplexers and multi-inputs • Unfortunately we do not have time to discuss the fullest implications of this important topic. • Interested students should read advanced chapters of Mano (Chapter 6 and higher).

14. Register Transfer • The internal hardware organization of a digital computer is best defined by specifying: • The set of registers it contains and their function • The sequence of microoperations performed on the binary data stored in the registers • The control that initiates the sequence of microoperations

15. Register Transfer R2 R1 • Notations and conventions: • Copy (ie. transfer) all data from one register (R1) to another (R2). • May be parallel or serial, but we do not need to ask R2 = R1 :: Use ‘=‘ for print convenience

16. Register Transfer R : High Low R1 7 6 5 4 3 2 1 0 (a) Complete Register R1 (b) Individual bits within R, such as R(0-7), R(15), R(L) 15 0 15 8 7 0 R2 PC (H) PC (L) (c) Numbering of bits in R2 (d) PC register divided into a High and a Low part • Notations and conventions: • If we intend to copy only a portion of data it is important to specify precisely where the data is located within the storage.

17. Register Transfer • Notations and conventions: • Conditional transfer • If ( P = = 1) then ( R2 R1 ) • This can be rewritten in the compact form: • P : R2 R1 • Finally, we can combine several operations in parallel: • T : R2 R1 , R4 R3 Parallel operations in hardware must be carefully checked for consistency to ensure they are sensible (achievable) and not just nonsense.

18. Memory • RAM storages are typically constructed as a single unit called a byte. • Although the standard storage unit for data is 8-bits (flip-flops), additional bits are used for a variety of purposes • especially error checking (Hamming Codes) • Each byte is located at a fixed address • Starts at address 0 and increases contiguously up to a maximum address, usually a power of 2 • Review lecture on multiplexers as address selectors enabling data transfer from selected bytes • The byte is called the smallest unit of addressable memory.

19. Memory Transfer • We reserve the letter M to denote volatile memory (ie. RAM) • Data in memory needs to be referenced by its location, or address • M[address] :: refers to the data stored at “address” • M[04C8] :: refers to the data stored at address 04C8 • M[AR] :: refers to the data stored at the address which is itself stored in the register AR (address register) Read operation : DR = M[AR] Write operation : M[AR] = DR

20. Microoperations • Register transfer microoperations transfer binary data from one register to another register. • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers. • Logic microoperations perform bit manipulation operations on non-numeric data stored in registers. • Shift microoperations perform shift operations on data stored in registers. Micro-operations are considered fundamental, or primitive (usually atomic) operations carried out in the CPU or elsewhere.

21. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

22. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

23. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

24. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

25. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

26. Arithmetic Microoperations • Multiple operations can be multiplexed together • Adder-Subtractor • Shift Left/Right • Logical • Arithmetic • Increment/Decrement • Load • And so on ….

27. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

28. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers.

29. Arithmetic Microoperations • Arithmetic microoperations perform arithmetic operations on numeric data stored in registers. Note that S1 and S2 are multiplexer selector inputs, whereas Cin is a separated input.

30. Logic Microoperations • Logic microoperations perform bit manipulation operations on non-numeric data stored in registers.

31. Logic Microoperations 0 4 1 1 1 2 2 1 2 2 2 3 3 3 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 • Consider all possible bit operations involving 2 inputs

32. Logic Microoperations • By labeling each possible operation we derive the following table.

33. Logic Microoperations • Refer to Mano • Multiplexed Logic Circuit (Figure 4.10) • Applications discussion, pages 11-113

34. Shift Microoperations • Shift microoperations perform shift operations on data stored in registers.

35. Shift Microoperations Shift left High order Bit Loss Low Order Input 0 Shift right High order Input 0 Low Order Bit Loss • Shift microoperations perform shift operations on data stored in registers.

36. Shift Microoperations Circular shift left High order to Low order Low order from High order Circular shift right High order From Low order Low order to High order • Shift microoperations perform shift operations on data stored in registers.

37. Shift Microoperations Arithmetic shift left High order Bit Loss Low Order Input 0 Arithmetic shift right High order Input High order Low order Bit Loss • Shift microoperations perform shift operations on data stored in registers.

38. Shift Microoperations • Shift microoperations perform shift operations on data stored in registers.

39. Shift Microoperations 0 Load 1 Complement 2 shl 3 shr 8x1 4 cil MUX 5 cir 6 ashl 7 ashr E Enable S2 S1 S0 Assume registers have L bits, each represented by a D flip-flop. F(i) ~F(i) i=0?0:F(i-1) i=L-1?0:F(i+1) F( (L+i-1)%L ) F( (L+i+1)%L ) i=0?0:F(i-1) i=L-1?F(L):F(i+1) D Q FF(i) F(i) REGISTER SELECTION CONTROL

40. Shift Microoperations 0 Load 1 Complement 2 shl 3 shr 3x8 4 cil DEC 5 cir 6 ashl 7 ashr E Enable S2 S1 S0 Example: L = 5 SHR :: F(4) = 0 F(3) = F(4) CIR :: F(4) = F( (5+4+1)%5 ) = F(0) F(3) = F(4) ASHR :: F(4) = F(4) F(3) = F(4) Assume registers have L bits, each represented by a D flip-flop. F(i) ~F(i) i=0?0:F(i-1) i=L-1?0:F(i+1) F( (L+i-1)%L ) F( (L+i+1)%L ) i=0?0:F(i-1) i=L-1?F(L):F(i+1) D Q FF(i) F(i)

41. Arithmetic Logic Shift Unit • Mano discusses a multi-stage circuit • Arithmetic stage • Logic stage • Multiplexed selection of operation • Read • Accompanying text

42. More Advanced Microoperations • The following topics are discussed later in Mano (3d Edition Chapters 6-10) and will be studied in the course 60-460 (Advanced Architecture). • Integer Multiplication & Division • Floating Point Architectures • FP Register design • FP Microoperations • Input/Output Architectures • The discussion in the lecture is oral and conceptual. There are no points discussed that are important for examinations – this is optional material that will not be tested.

43. Three-State Buffers Output Y Input A C Control • An important device called a 3-state bus buffer has been developed. • Basically a capacitor with an impedance trigger • Capacitors can hold a charge (equivalently, a voltage level) for a long time until an event triggers the release of the charge (equivalently, allows a voltage level to pass onto a connecting wire). Impedance refers to a property of electrical circuits, where current does not flow between connected wires or gates unless the impedances match in the connected sub-systems. • Thus, if C=0, no signal flows from A to Y. Y is therefore not defined. • However, if C=1, impedances are matched and signal flows from A to Y. The value at Y is then A.

44. Three-State Buffers Bus line for bit K R0 R1 R2 R3 { S0 S1 E 0 1 2 3 2x4 DEC (K) Select Enable • 3-state bus buffers are often used at the outputs of storage flip-flops. • Essentially, the buffer unit “holds” the value stored in the FF. • Holding is useful for synchronizing enabling of parallel circuits • The buffer unit can be used along with a Decoder unit as a replacement for an address multiplexer. • This is an alternative approach.

45. Three-State Buffers Bus: R2(K) R0 R1 R2 R3 { S0 S1 E 0 1 2 3 2x4 DEC (K) Select Enable • 3-state bus buffers are often used at the outputs of storage flip-flops. • Essentially, the buffer unit “holds” the value stored in the FF. • Holding is useful for synchronizing enabling of parallel circuits • The buffer unit can be used along with a Decoder unit as a replacement for an address multiplexer. • This is an alternative approach. 0 1 1

46. Summary • We introduced Mano’s basic CPU architecture • Registers • Bus • We discussed Register and Memory Transfer and introduced a language suitable for description and design • We presented several example applications of RTL/MTL for Microoperations • Arithmetic • Logic • Shift • We discussed briefly more advanced applications