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Why Johnny Can’t Code Preparing Engineers for Billion Gate Designs

This interview with Mike Keating discusses the challenges of training engineers for large-scale hardware designs and the importance of structured code and code size in improving design quality and efficiency.

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Why Johnny Can’t Code Preparing Engineers for Billion Gate Designs

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  1. Why Johnny Can’t CodePreparing Engineers for Billion Gate Designs Mike Keating

  2. Interview Question A D C B 2x the processes = 2x the complexity clk assign D = A && B; always @ (posedgeclk) begin C <= D; end always @ (posedgeclk) begin C <= A && B; end

  3. Why Code Size Matters Designers inject approx. 1 defect per 10 lines of code Excellent code ships with ~1 defect per KLOC 100M LOC

  4. Typical RTL Code

  5. Unstructured Verilog Code assign … always @(*) … always @(*) … always_ff @ (posedgeclk …) … assign … always @(*) … assign … always_ff @ (posedgeclk …) … always @(*) …

  6. Unstructured Verilog Code assign … always @(*) … always @(*) … // get packet always_ff @ (posedgeclk …) … assign … always @(*) … assign … // send packet always_ff @ (posedgeclk …) … always @(*) … It’s like majoring in assembly language programming with emphasis on the “goto” statement

  7. Model of Structured Code void bar () { f1 (); } void foo () { bar (); } main () { foo (); } function f (); … endfunction task get_packet (); my_var2 <= g (…); endtask task send_packet (); my_var1 <= f (…); endtask always_ff @ (posedgeclk …) begin get_packet (); send_packet (); end class bar_class () { …; } class foo_class () { … } main () { constructors for classes … } module bar_module (); …; endmodule module foo_module (); … endmodule top_module (); instantiate modules … endmodule Too much code? Acts as “main”

  8. Code Size Counts – DCT Example

  9. Code Size Counts – DCT Example

  10. Code Size Counts – DCT Example

  11. Real-time reactive designs (USB, PCI Express) require a more sophisticated form of structured design

  12. Structured Sequential Code - FSMs + { f (state, inputs) } State machine along with a set of combinational functions

  13. High Level Synthesis #include<stdio.h> #include<stdlib.h> int block[8][8]; void dct(){ int y,x,u,v; int reg[8]; /* Horizontal */ for(y=0;y<8;y++){ for(x=0;x<8;x++) reg[x]=0; for(x=0;x<8;x++){ for(u=0;u<8;u++){ v=block[y][x]*c[x][u]; v+=2048; v>>=12; if(s[x][u]) v=-v; reg[u]+=v; } } Set of Arithmetic Functions State Machine

  14. Hierarchical State Machines + { f (state, inputs) } Hierarchical State machine along with a set of combinational functions

  15. Hardware Model of Structured Code function f (); … endfunction function g (); … endfunction always_ff @ (posedgeclk …) case (state) IDLE: …; S0: begin if (f(input_x)) doit_x(); if (doit_x_done) state<= S2; end endcase task doit_x(); doit_x_done = 0; case (doit_x_state) S0: … Sn: begin … doit_x_done = 1; doit_x_state = S0; end endcase } Sub_state Machines

  16. USB Example – DMA Processing About 28 pages – too big! Massive Concurrency Impossibly large state space

  17. USB Example – DMA Processing 1/3 smaller Much Less Concurrency Dramatically smaller state space

  18. Improving RTL Code

  19. What Students Need to Know • How to use structure to reduce code size and design complexity • SystemVerilog • Structs, enumerated types, interfaces • Functions, tasks • How to measure state space and understand cost of verifying complex designs • How to design and code hierarchical state machines to minimize state space

  20. What EDA needs to Do

  21. More Interview Questions No good encapsulation mechanism always @ (posedgeclk …) begin W <= ……..; end always @ (posedgeclk …) begin X <= ……..; end always @ (posedgeclk …) begin Y <= ……..; end always @ (posedgeclk …) begin Z <= ……..; end A C E Silly B D Where’s the latch? always @ (*) begin C = A && B; E = C && D; end Silly Does not model hardware (System)Verilog is not a good hardware design language – just better than VHDL or SystemC

  22. Domain Specific Languages

  23. (System)Verilog is NOT Domain Specific for Design Verilog: wires reg’s (which are not registers) SystemVerilog bit logic Both: whether a variable is a flop, latch or logic gate is determined by how it is used bit_ff bit_comb state_machine reg d; always_comb d = a | b;

  24. Raising Abstraction of Design General Purpose, High Level Modeling Languages C++/SystemC Design-specific language for multiple levels of abstraction Gap is too big language, methodology, tools SystemVerilog General Purpose Simulation Language

  25. It’s All Mission Critical

  26. It’s all about Code Thank You Source: IBS Design Implementation 7/09

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