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Synthesis of synchronous elastic architectures. Jordi Cortadella (Universitat Polit è cnica Catalunya) Mike Kishinevsky (Intel Corp.) Bill Grundmann (Intel Corp.). Network of Computing Units. Out. In. B3. B1. B2. Network of Computing Units. Out. In. B3. B1. B2.
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Synthesis of synchronouselastic architectures Jordi Cortadella (Universitat Politècnica Catalunya) Mike Kishinevsky (Intel Corp.) Bill Grundmann (Intel Corp.)
Network of Computing Units Out In B3 B1 B2
Network of Computing Units Out In B3 B1 B2
Network of Computing Units Out In B3 B1 B2
Latency-insensitive (elastic) system Out In B3 B1 B2 Every block onlymakes one step when all inputs are valid
Why • Scalable • Modular (Plug & Play) • Tolerance to variable latency • Communication • Computation • Not asynchronous • Use existing design paradigms • CAD tools
Outline • The cost of elasticity • SELF: an elastic protocol • Basic implementation (linear pipelines) • General netlists (forks and joins) • Formal models and verification • Synthesis of elastic architectures • Related work
Area, power and latency Gated clock Control Valid Valid Stop Stop CLK What’s the cost ofelasticity? Elastic block Core Data Data
Communication channel sender receiver Data Data Long wires: slow transmission
Data Pipelined communication sender receiver Data
Data Pipelined communication sender receiver Data
Data Pipelined communication sender receiver Data How about if the sender does not always send valid data?
The Valid bit sender receiver Data Data Valid Valid
Data Valid The Valid bit sender receiver Data Valid
Data Valid The Valid bit sender receiver Data Valid
Data Valid The Valid bit sender receiver Data Valid
Data Valid The Valid bit sender receiver Data Valid How about if the receiver is not always ready ?
sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 0 The Stop bit
sender receiver Data Data Valid Valid Stop Stop 0 0 0 1 1 The Stop bit
sender receiver Data Data Valid Valid Stop Stop 0 0 1 1 1 The Stop bit
sender receiver Data Data Valid Valid Stop Stop 1 1 1 1 1 The Stop bit Back-pressure
sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 1 The Stop bit Long combinational path
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage)
sender receiver shell shell main main main pearl pearl V V V V S S S S aux aux aux Carloni’s relay stations (double storage) • Handshakes with short wires • Double storage required
Proposal: an elastic protocol • SELF (Synchronous ELastic Flow) • Simple and provably correct • Data-path with no overhead in: • Area • Latency • Energy • Negligible control overhead • Fine-grain elasticity
Flip-flops vs. latches sender receiver FF FF 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle
Flip-flops vs. latches sender receiver H L H L 1 cycle Flip-flops already have a double storage capability, but …
Flip-flops vs. latches sender receiver H L H L 1 cycle Not allowed in conventional FF-based design !
H L H L Flip-flops vs. latches sender receiver 1 cycle Let’s make the master/slave latches independent
H L H L Flip-flops vs. latches sender receiver ½ cycle ½ cycle Let’s make the master/slave latches independent Only half of the latches (H or L) can move tokens
Elastic buffer keeps datawhile stop is in flight Cannot be done withSingle Edge Flops without double pumping Use latches inside MS W1R1 W2R1 W1R2 Carloni’s relay station belongs to this class W2R2
SELF (linear communication) sender receiver Data Data En En En En V V V V Valid Valid 1 1 1 1 Stop Stop S S S S
SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S
SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S
SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S
SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S
SELF sender receiver Data Data En En En En V V V V 1 Valid Valid 0 Stop Stop S S S S