Design and Optimization of Synchronous Elastic Systems

Part 2: Synchronous Elastic Systems Jordi Cortadella and Mike Kishinevsky 28th Int. Conf. on Application and Theory of Petri Nets and Other Models of Concurrency Siedlce, Poland, June 25, 2007 Universitat Politecnica de Catalunya Barcelona, Spain IntelStrategic CAD Labs Hillsboro, USA

Synchronous elastic systems also called • Latency tolerant systems or • Latency insensitive systems • We use term “synchronous elastic” since better linked to asynchronous elastic

Basics of elastic systems Early evaluation and performance analysis Optimization of elastic systems and their correctness Agenda of Part 2

What and Why Intuition How to design elastic systems Converting synchronous system to elastic Micro-arch opportunities Marked Graph models Performance evaluation I

Token (of data) Synchronous Stream of Data … 4 7 1 … Clock cycle 2 1 0

Token Bubble (no data) Synchronous Elastic Stream … 4 7 1 … Clock cycle 2 1 0 … Clock cycle 5 4 3 2 1 0 … 1 7 4

Synchronous Circuit Latency = 0 … … + 4 7 1 … 4 8 3 0 1 2

Synchronous Elastic Circuit Latency = 0 … … + 4 7 1 … 4 8 3 0 1 2 … … 4 + 7 1 e … 3 4 8 0 1 2 Latency can vary

Ordinary Synchronous System A C A C = D D B B Changing latencies changes behavior

Synchronous Elastic (characteristic property) A C A C e e e e e = D D B B e e e e Changing latencies does NOT change behavior = time elasticity

Why • Scalable • Modular (Plug & Play) • Better energy-delay trade-offs (design for typical case instead of worst case) • New micro-architectural opportunities in digital design • Not asynchronous: use existing design experience, CAD tools and flows

Example of elastic behavior

ALU 5 6 1 2 3 1 2 3 4 4

ALU 6 1 2 3 4 2 3 4 5 5

ALU 1 2 3 4 5 3 4 5 6 6

ALU 2 3 4 5 6 4 5 6 1 1

ALU 3 4 5 6 1 5 6 1 2 2

ALU 4 5 6 1 2 6 1 2 3 3

ALU 5 6 1 2 3 1 2 3 4 4 ?

ALU 1 2 3 4 4 3 2 6 5 ?

Not valid ALU 1 2 3 4 4 3 2 6 5 5 Stop ! ? Join

ALU 1 2 3 4 4 3 2 6 5 5 Not valid ? Stop !

ALU 1 2 3 4 4 3 2 6 5 5 Not valid ? Lazy (stop) Stop !

ALU 1 2 3 4 4 3 2 6 5 5 ? Lazy (stop)

ALU 1 2 3 4 4 3 6 5 5 ? Lazy (stop)

ALU 1 2 3 4 4 3 6 5 5 6 ? Stop

ALU 1 2 3 4 4 3 6 5 5 6 ?

ALU 1 2 3 4 4 6 5 5 6 ?

ALU 2 3 4 4 5 6 6 5 1 1 ?

ALU 4 5 5 6 6 1 1 3 2 ?

How to design elastic systemsWe show an example of the implementation: SELF = Synchronous Elastic Flow Others are possible

Reminder: Memory elements. Transparent latches Q Q D D L H En En Active low: En = 1 (opaque): Q = prev(Q) En = 0 (transparent): Q = D Active high: En = 0 (opaque): Q = prev(Q) En = 1 (transparent): Q = D 36

Reminder: Memory elements. Flip-flop Q D Q L H D FF CLK CLK CLK D Q 37

Reminder: Clock cycle = two phases 0 delay abstraction = L H 0 delay abstraction 0 delay abstraction 38

Elastic channel protocol not Valid Valid * Stop Retry Idle Sender Receiver Data Valid * not Stop Valid Transfer Stop

Sender Receiver Elastic channel protocol * D D * C C C B * A Data Data 0 1 1 0 1 1 1 1 0 1 Valid Valid 0 0 1 0 0 1 1 0 0 0 Stop Stop Transfer Retry Idle

Elastic buffer keeps data while stop is in flight Cannot be done withSingle Edge Flops without double pumping Can use latches inside Master-Slave W1R1 W2R1 W1R2 W2R2

Communication channel sender receiver Data Data Long wires: slow transmission

Data Pipelined communication sender receiver Data What if the sender does not always send valid data?

The Valid bit sender receiver Data Data Valid Valid What if the receiver is not always ready ?

sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 0 The Stop bit

sender receiver Data Data Valid Valid Stop Stop 1 1 1 1 1 The Stop bit Back-pressure

sender receiver Data Data Valid Valid Stop Stop 0 0 0 0 1 The Stop bit Long combinational path

Cyclic structures Data Valid Stop Combinational cycle One can build circuits with combinational cycles (constructive cycles by Berry), but synthesis and timing tools do not like them

Design and Optimization of Synchronous Elastic Systems