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ARM, SPARC, x86 ARM (Advanced RISC machine) Load/store architecture

ARM, SPARC, x86 ARM (Advanced RISC machine) Load/store architecture 65 instructions (all fixed length – one word each = 32 bits) 16 registers Comparison and contrast of ARM, SPARC, and Intel x86 Similarities: 8-bit bytes (allows representation of ASCII-encoded character)

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ARM, SPARC, x86 ARM (Advanced RISC machine) Load/store architecture

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  1. ARM, SPARC, x86 ARM (Advanced RISC machine) • Load/store architecture • 65 instructions (all fixed length – one word each = 32 bits) • 16 registers Comparison and contrast of ARM, SPARC, and Intel x86 Similarities: • 8-bit bytes (allows representation of ASCII-encoded character) • Byte-addressable memory (address down to individual character)

  2. ARM, SPARC, x86 Similarities: • 8-bit bytes (allows representation of ASCII-encoded character) • Byte-addressable memory (address down to individual character) • two's complement for signed integers floating point follows IEEE standard arithmetic, logical, and shift operations branching and calling instructions condition codes used for branch decisions stack frame support (sp, fp/bp) for procedure calls can be pipelined and have superscalar, multithreaded, and multicore implementations

  3. ARM, SPARC, x86 Differences (cont’d):

  4. ARM, SPARC, x86 Differences (cont’d):

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