1 / 10

ucore arm port

ucore arm port. j ianfei wang. ARM. Advanced RISC Machine Remember TEC-2008? s everal types of architecture, from ARMv1 to ARMv7 mainly used in embedded system developing on S3C2410, with an ARM7 core, ARMv4T architecture will be compared with X86 later. progress.

padma
Download Presentation

ucore arm port

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ucorearm port jianfei wang

  2. ARM • Advanced RISC Machine • Remember TEC-2008? • several types of architecture, from ARMv1 to ARMv7 • mainly used in embedded system • developing on S3C2410, with an ARM7 core, ARMv4T architecture • will be compared with X86 later

  3. progress • week 4: tool chains setup, hello world • week 5: boot loader, simple kernel, cprintf • week 6: interrupt. basic atomic operations • week 7: study MMU, no much progress • week 8: buddy pmmand slab. • week 9: finish lab2(vmm) and refactor code.

  4. problems • expected • dev environment • boot • interrupt • memory management • unexpected • div/mod • atomic • memory

  5. tool chains • ArchLinux • cross-arm-elf-gcc-base 4.5.2 • cross-arm-elf-binutils 2.21 • cross-arm-elf-gdb 7.2 • skyeye 3.2 rc

  6. booting • x86 • BIOS is responsible for loading 1st sector • need a boot loader to load the rest of the OS • arm • storage(usually Flash Memory) is mapped to memory address • can boot directly from it • still need a loader to load the elf kernel.

  7. interrupt • ARM has many modes, not just ring 0/3 in x86 • SVC, UND, ABT, IRQ, FIQ • each mode has its own SP register (and other regs) • IO operations managed by page permissions • interrupt vector at address 0x0 • hardware interrupt goes into IRQ/FIQ mode • software interrupt goes into a SVC mode

  8. interrupt (cont.) • controlled by a range of special memory address • read a special memory address to determine which interrupt happened • write special memory address to disable/enable specific interrupt • use a bit in CPSR (current program status register) to enable/disable hardware interrupt • allow re-enter by enable interrupt after proper setup and disable interrupt before return

  9. memory management • no GDT, pure paging • have MMU as a coprocessor • page table • one level (1MB page) • two level (1k to 64K pages) • modify coprocessor register to control MMU • load the L1 page table address • enable/disable MMU

  10. unexpected • div (needed by cprintf) • stole code from u-boot and Linux kernel • atomic • no atomic instructions (not like x86) • disable interrupt to achieve atomicity • carefully stole code from Linux kernel • non-continuous memory, need a better way for PMM

More Related