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Simultaneous Clock and Data Gate Sizing Algorithm with Common Global Objective

Simultaneous Clock and Data Gate Sizing Algorithm with Common Global Objective. Gregory Shklover , Ben Emanuel Intel Corporation MATAM, Haifa 31015, Israel. Outline. Introduction Gate sizing by lagrangian relaxation Combined clock and data sizing Clock sizing by dynamic programming

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Simultaneous Clock and Data Gate Sizing Algorithm with Common Global Objective

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  1. Simultaneous Clock and Data Gate Sizing Algorithm withCommon Global Objective Gregory Shklover, Ben Emanuel Intel Corporation MATAM, Haifa 31015, Israel

  2. Outline • Introduction • Gate sizing by lagrangian relaxation • Combined clock and data sizing • Clock sizing by dynamic programming • Algorithm analysis • Experimental results

  3. Introduction • Given a gate-level circuit and a standard cell library, the goal of such optimization is to find gate sizes that would yield best combination of total circuit power, performance and area. • Data gates • implement the logical function of the block • Clock gates • distributing common synchronization signal to different state elements in the circuit

  4. Separation reasons • Design methodology • Data: best performance vs power or area • Clock: meet minimum skew and skew variability • Structure • Data: DAG • Clock: tree (Dynamic programming) • Problem classification • Data: convex • Clock: non-convex

  5. Contribution • Combine clock and data sizing decisions to solve a common global objective • Use Dynamic Programming algorithm to optimally solve the clock-related part of the relaxed objective

  6. Gate sizing by lagrangian relaxation • Minimizes the following objective:

  7. Gate sizing by lagrangian relaxation • Simplified formulation:

  8. LR with skew optimization • speeds up aclk at FF1 by up-sizing of gate A • delay aclk at FF2 by down-sizing gate B.

  9. Combined clock and data sizing • Consider the set of clock gates • Integrating these into Objective • expanding each as clkas a sum of delays from the root of the clock tree to the corresponding leaf

  10. Combined clock and data sizing

  11. Clock sizing by dynamic programming • DP algorithm is required to find clock gates sizes that minimize the following objective:

  12. Clock sizing by dynamic programming

  13. Dynamic programming • Set of solutions per tree node n • c is the associated downstream capacitance • obj is the corresponding objective value • Pruning criterion

  14. Dynamic programming • Leaf nodes: • Solution merge: • Gate sizing:

  15. Additional considerations • Side load effect • Approximation+convergence • Input slews

  16. Algorithm analysis • Complexity • k-Sampling • the complexity for the DP algorithm: • Convergence • Cooling concept from simulated annealing • Optimality • global optimality is not theoretically guaranteed.

  17. Experimental results

  18. Experimental results

  19. Summary • simultaneous clock and data gate sizing optimization • applicable to wire sizing and buffer insertion. • Probably could extend this method to handle simultaneous gate sizing and clock tree synthesis.

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