WP4 M24 Deliverables Catania, Nov. 10 th , 2010

1. WP4 M24 DeliverablesCatania, Nov. 10th, 2010 Architectural to system level: modeling, analysis and design WP4 Meeting

2. Task T4.1: Variability-aware Design • Partners: LETI, UPC • Task leader: Edith BEIGNE (LETI) • Definition and development of (self-) adaptive compensation and optimization techniques to cope with increasing PV variations • Development of new adaptive voltage and frequency scaling (AVFS) techniques which can be exploited either after testing or at run-time WP4 Kick-off Meeting

3. Task T4.1: Variability-aware Design • LETI will develop a network of distributed on-chip controllers to optimize the SoC global performance by exploiting the resource monitors designed in WP3 • Distributed and interconnected controllers will be used to adjust locally and dynamically the power supply level, threshold voltages, and operating frequency, while satisfying the global system constraints • UPCwill define and design specific functional blocks for AVFS such as monitors and level shifters to tune the operating frequency and power supply levels and to connect different voltage islands • A test vehicle will be taped out with the designed sensor and level shifter circuits WP4 Kick-off Meeting

4. Task T4.2: Variation-tolerant, Robust, Low-noise and Low-EMI Architectures/Micro-architectures • Partners: TMPO, LETI, ELX, POLI, ST I, TEKL • Task leader: Jordi CORTADELLA (ELX) • Development and design of advanced macro-blocks for robust and reliable systems • Development and design of adaptive architectures based on asynchronous and de-synchronization techniques for: • Computational units and memories • On-chip communication schemes based on GALS paradigm • Synthesis of PV-tolerant asynchronous/de-synchronized functional blocks and architectures for low-EMI design WP4 Meeting

5. Task T4.2: Variation-tolerant, Robust, Low-noise and Low-EMI Architectures/Micro-architectures • TMPO will design and characterize PV-tolerant, low-noise and low-EMI asynchronous macro-blocks • LETIwill study asynchronous and de-synchronized communication schemes in GALS-type architectures • Quasi-delay-insensitive (QDI) and de-synchronized approaches will be evaluated in a NoC • Adaptive communication architectures based on globally asynchronous or de-synchronized communication will be optimized for PV variations • ELXwill develop a complete automatic design flow for the synthesis of asynchronous circuits either from RTL specifications or from a post-placement gate-level netlists WP4 Meeting

6. Task T4.2: Variation-tolerant, Robust, Low-noise and Low-EMI Architectures/Micro-architectures • POLI will develop a new asynchronous synthesis prototype tool starting from untimed (or partially-timed) SystemC description • New synthesis techniques to improve the performance and (by using dynamic voltage scaling) reducing power consumption • ST I will provide the industrial test cases and design flows to validate these novel asynchronous design methodologies • TEKL will develop the methodology and support for integrating its novel power shaping optimization technology for EMI reduction into existing synchronous mainstream design flows WP4 Meeting

7. Task T4.3: Design of Reliable Systems • Partners: THL, NMX, ST F, ISD • Task leader: Stratos POLITIS (ISD) • Design of highly reliable analog, mixed-mode, digital, and NVM systems based on unreliable foundations subject to large PV variations and degradation • New mechanisms to recognize faulty devices and structures before the overall system collapses will be developed along with procedures to reconfigure the system so that it continues operating, although at a lower frequency, thus allowing a graceful degradation WP4 Meeting

8. Task T4.3: Design of Reliable Systems • THL and ST F will study and develop a parallel architecture for safety-critical applications compatible with PV variability for robust and time-predictable design • Multi-core architecture will be based on fault detection, isolation, and communication dynamic reconfiguration • Design of a processing core for a parallel architecture with real-time and time-predictable capabilities • In particular ST F will extend Spidergon STNoC to cope with the requirements of the multi-core architecture • ISDwill design highly-reliable analog, mixed-mode, and digital blocks implemented in a moderately reliable CMOS process. Moreover, ISD plans to investigate fault-tolerant routing, as well as fault diagnosis and dynamic reconfiguration schemes • NMXwill design highly-reliable and fault-tolerant NVM systems WP4 Meeting

9. Task T4.4: Design of Regular Architectures and Circuits for High Manufacturability and Yield • Partners: TMPO, UPC, ST-I, UNBO • Task leader: Roberto CANEGALLO (ST I) • Design of customizable circuits, macro-blocks, and architectures based on regular structures to improve manufacturability and predictability WP4 Kick-off Meeting

10. Task T4.4: Design of Regular Architectures and Circuits for High Manufacturability and Yield • TMPO will design variability-tolerant asynchronous functional blocks using regular structures to evaluate the yield improvement, while satisfying low-noise/low-EMI requirements • UPCwill develop a via-configurable regular transistor array to improve parametric yield, and manufacturability • STIwill design customizable via-programmable macro-blocks and mask-programmable IPs suitable for a fast and efficient SoC design and mapping on regular transistor arrays • UNBOwill design a customizable architecture for homogeneous multi-threading based on modular elementary computational blocks • The silicon structure for architectural mapping will be the regular transistor array developed in cooperation with ST I WP4 Kick-off Meeting

11. Task T4.5: Distributed reconfigurable PV-robust architectures • Partners: THL, LIRM • Task leader: Philippe Bonnot (THL) • Programming methods and tools for predictable and PV-robust MPSoC computing architectures will be developed to consider PV variations at the software/system level, since specific formalisms for execution-time management for critical applications embedded into multi-core architectures are required as early as possible in the design cycle WP4 Kick-off Meeting

12. Task T4.5: Distributed reconfigurable PV-robust architectures • THL will develop programming methods and tools for predictable processing architectures to take into account PV variations • LIRMwill study self-adaptive mechanisms to allow application task run-time remapping onto a distributed reconfigurable multi-core architecture, maintaining a given functionality with the same level of performance under PV variability • The remapping policy will be based on the information obtained from on-die monitors WP4 Kick-off Meeting

13. M24 Deliverables WP4 Meeting

14. M24 Deliverables WP4 Meeting

15. WP4 Domain Overview per Task and Partner MODERN General Meetings Catania, Nov. 9 & 10, 2010

16. WP4 Technology Overview per Task and Partner MODERN General Meetings Catania, Nov. 9 & 10, 2010

17. WP4 Cooperations • In T4.1 collaboration between LETI and ST F on technology transfer • In T4.1 cooperation between LETI and UPC on the temperature monitoring activity, and to coordinate the activities of both institutions in MODERN • In T4.1 cooperation between ELX and UPC on voltage variation measurements across chip • In T4.2 cooperation between ELX, POLI, and ST I on the design flow for desynchronization and on EMI reduction techniques • In T4.2 cooperation between TEKL and ST I on the power shaping methodology for EMI reduction and flow definition and integration of TEKL’s tool into ST design flow • In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic implementation MODERN General Meetings Catania, Nov. 9 & 10, 2010

18. WP4 Cooperations • In T4.3 common research activities and cooperation between ISD and THL, and between THL and ST F • In T4.3 cooperation between ST F and UNBO has started on STNoC technology • In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the impact of regular design • In T4.4 ST I and UNBO are cooperating on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths • In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability • In T4.5 cooperation between LIRM and ST F on MPSoC fault tolerance MODERN General Meetings Catania, Nov. 9 & 10, 2010

19. WP4 Link w/- Other MODERN’s WPs WP5 WP3 WP4 UPC, LETI UPC, LETI T5.2 T3.3 T4.1 ST I LETI, TMPO T5.3 T4.2 T3.4 THL T4.3 UPC, TMPO, ST I ST I T4.4 THL, LIRM T4.5 MODERN General Meetings Catania, Nov. 9 & 10, 2010

20. Published Papers • F. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010. • I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc.VARI, May 2010 • C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres,“A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc.Intl. Symp. on VLSI, Jul. 2010. • C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc.DATE, Mar. 2010. • J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in Proc. VARI 2010, May 2010. • J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc. Intl. Conf. on Integrated Circuits Design and Technology, Jun. 2010. • C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010. • I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl. Symp. on VLSI, Jul. 2010. • I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep. 2010. • N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010. • M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010. • N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010. • N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010. MODERN General Meetings Catania, Nov. 9 & 10, 2010

21. WP4 Summary • Four WP4 meetings to prepare M24 deliverables • F2f meetings ELX/UPC on July 12th and 19th and on October 5th, 2010. • Web meeting Sep. 17th • F2f meeting ST Catania Nov. 9th • Demonstrators • System MPSoC platform, with task migration, failure analysis, power optimization considering variability effects, and HW implementation of several blocks to propose online optimization – LIRM T4.5 • All M24 deliverables are on track • No major criticality detected/reported by task leaders and partners MODERN General Meetings Catania, Nov. 9 & 10, 2010