THERMINATOR Kick-Off Meeting Catania, February 26 th 2010

1. THERMINATOR Kick-Off MeetingCatania, February 26th 2010 WP5 - Modeling and Design of Discrete Components

2. List of Workpackages • WP1:Technology Characterization, Tool Requirements and Test Case Identification • WP2:Process, Device and Compact Modeling • WP3:Modeling and Design of Digital Components • WP4:Modeling and Design of Analog/RF Components • WP5:Modeling and Design of Discrete Components • WP6:Package Modeling, System and Board-Level Simulation and Design Exploration • WP7:Validation, Demonstration and Evaluation • WP8:Dissemination, Training, Exploitation, Roadmapping and IPR Management • WP9:Project Management

3. WP5 - Modeling and Design of Discrete ComponentsLeader: Giuseppe Greco (ST-I) WP5 focuses on discrete components, the target is the development of a thermal-aware modeling framework covering thermal modeling issues and estimation/simulation aspects that can be found in the industrial context. the framework will: • Enable the extraction of the thermal finite element models of an elementary unit cell of a power device with consolidated extraction flows based on custom and commercial tools • Allow the creation of a fully coupled thermal netlist exploiting the previously extracted models. • Enable the simulation, at the circuit level, the extracted netlist in short times. • Facilitate the collection of post-process simulation information • Enable the estimation of the thermal impedance Zth(t) for duration times close to few hundreds of nanoseconds.

4. Pert Diagram Technology Characterization, Tool Requirementsand Test Case Identification WP1 Process data Process, Device and Compact Modeling WP2 Tool requirements Process and device models Project Management Dissemination, Training, Exploitation, Roadmapping and IPR Management Modeling and Design of Digital Components Modeling and Design of Analog/RF Components Modeling and Design of Discrete Components Test cases WP3 WP4 WP5 Models, design techniques and tools Package Modeling, System and Board-LevelSimulation and Design Exploration WP6 Simulation and exploration framework Validation, Demonstration and Evaluation WP8 WP9 WP7

5. WP5 Tasks • Task 5.1: Thermal modeling of discrete componentsParticipants: SNPS-CH, ST-I, IMEC, UNIBO • Task 5.2: Validation of modeling framework for discrete componentsParticipants: ST-I, IMEC, FHG Task leaders to be defined!

6. WP5 Deliverables 5.1.1 - Elementary cell compact model and parameter extraction methodology (SNPS-CH) 5.1.2 - Extraction methodology for the creation of a thermal model (ST) 5.1.3 - EDA tool enhancement to create the thermal layer to be overlapped to the basic netlist (ST) 5.1.4 - Thermal-aware modeling framework (ST) 5.2.1 - Validation results of thermal-aware modeling framework (IMEC)

7. Work outline proposal • What to do? • Who has to do what?

8. What to do?Foresee electrical/thermal behavior of discrete power devices • The target is to be able to foresee, in pre-silicon phase, through a thermal-aware modeling framework, the complete electrical/thermal behavior of discrete power devices in order to define best design guidelines meant to reduce failures. Thermal Camera acquisition Total acquisition time: 40µs

9. What to do?State-of-the-art in discrete devices analysis in ST • PAN: Power MOS, IGBT Analysis flow • BAN,BANF: Distributed Modeling of • Power Bipolar Devices T. Biondi, G. Greco, G. Bazzano, S. Rinaudo “Distributed Modeling of High-Speed Silicon Power MOSFETs” Presentazione orale alla Riunione Annuale del Gruppo Elettronica - Naxos, 30 Giugno – 2 Luglio 2005 T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo “Analysis of the Internal Current Distribution in Power MOSFETs Operated at High Switching Frequency” Proceedings of MSED 2005 - 15th Workshop on Modeling and Simulation of Electron Devices, Pisa, Italy, 4-5 July 2005. T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo “Effect of layout parasitics on the current distribution of power MOSFETs operated at high switching frequency” Journal of Computational Electronics, vol. 5, no 2-3, pp. 149-153, July 2006. T. Biondi, G. Greco, M.C. Allia, S.F. Liotta, G. Bazzano, and S. Rinaudo “Distributed Modeling of Layout Parasitics in Large-Area High-Speed Silicon Power Devices” Power Electronics, IEEE Transactions on Volume 22, Issue 5, Sept. 2007 Page(s): 1847 - 1856 Digital Object Identifier 10.1109/TPEL.2007.904241. F. Fiorante, G. Greco, G. Nicosia, S. Rinaudo, G. Stracquadanio, “Automatic Layout Optimization of Power Mosfets Using An Effective Population-Based Algorithm”,2008 SIAM Optimization Conference - OP08, Boston, Massachusetts, USA, May 10-13, 2008 G. Greco, C. Rallo “XA Integration in Custom Power Mosfet Analysis Flow” Synopsys User Group, SNUG 2008, Boston, MA, USA, September 22 - 23, 2008. G. Greco, C. Rallo “XA Integration in Custom Power Mosfet Analysis Flow” Electronic Engineering (Korean language), magazine, 2009 December issue, pp. 117-127. T. Biondi, G. Greco, G. Bazzano, and S. Rinaudo “Method for modeling large-area transistor devices, and computer program product therefore” U.S. Patent N. 11/770,578 deposited in 28 June 2007 valid until 28 June 2027.

10. What to do?Distributed Modeling of discrete devices Matrix Extractor Module Eldo Netlister Device Layout Setting GUI Eldo Simulation .Chi2PanData Converter Self-Heating Thermal Maps PanData postprocessor Electrical Maps

11. What to do?Thermal analysis post process example

12. Device characterization Matrix generation Elementary cell modeling Performance analysis What to do?modeling flow

13. Where:Tjunction = junction temperature Pdiss = instantaneous power losses Zth(t)= thermal impedancejunction-to-case Tcas = case temperature What to do?Improvements to existing modeling flow ST state-of-the-art flow is based only on a basic thermal modeling flow that take into account only self-heating effect

14. What to do?How to approach the new strategy ST proposal is to define a new flow able to represents the true thermal behavior of the power device taking into account all coupling effects. Our proposal will impact on: • elementary cell modeling • cells array generation

15. source drain What to do? How to approach the new strategy Basic device layer already takes into account self-heating effect gate Elementary cell

16. source drain What to do? How to approach the new strategy A thermal layer will take into account heat propagation Temperature reference nodes gate Elementary cell

17. What to do? How to approach the new strategy A thermal layer will take into account heat propagation ?To de defined Thermal cell

18. What to do? How to approach the new strategy The thermal layer should be extracted starting from device layout and technology information. FEM or other kind of approaches could be used in order to synthesize a lumped thermal network.

19. Matrix Extractor ModuleThermal network extractor NEW Eldo Netlister Device Layout Setting GUI Eldo Simulation .Chi2PanData Converter Full Thermal Maps PanData postprocessor Electrical Maps What to do? How to approach the new strategy

20. Distributed model featuring thermal effect What to do? How to approach the new strategy • Framework Validation FEM simulations Thermo camera measurement

21. Work outline proposal • What to do? • Who has to do what? (only a ST-I proposal to be discussed with partners)

22. Who has to do what?Partner involvement proposal • D5.1.1 Elementary cell compact model and parameter extraction methodology D G S ST-I andSynopsys-CH teams are mainly involved in the extraction of basic cell on the pilot device chosen in WP1. Results of WP2 are important for completing this item.To de decided: other partner contributes could be evaluated, for instance, UNIBO and others? By June 2010 results are expected.

23. D T G S Who has to do what?Partner involvement proposal • D5.1.2 Extraction methodology for the creation of a thermal model with a T node. ST-I team is mainly involved in building an extraction methodology for the creation of a thermal model. Results of D5.1.1 are necessary to start with this item.To de decided:Other partner contributes could be evaluated, for instance, Synopsys-CH, UNIBO and others? By December 2010 first results are expected.

24. Who has to do what?Partner involvement proposal D5.1.3 EDA tool enhancement to create the thermal layer to be overlapped to the basic device layer ST-I, UNIBO and Synopsys-Ch teams are mainly involved in creating an extraction methodology for the creation of the thermal layer. To de decided:Other partner contributes could be evaluated, for instance, IMEC? By December 2011 first results are expected.

25. Who has to do what?Partner involvement proposal D5.1.4 Thermal-aware modeling framework matrix netlister conversion plot ST-Iteam is mainly involved in creating Thermal-aware modeling framework (EDA tools development). To de decided: Other partner contributes could be evaluated, for instance, Synopsys-CH and others? By December 2012 first results are expected.

26. Who has to do what?Partner involvement proposal D5.2.1 Validation results of thermal-aware modeling framework Distributed model featuring thermal effect FHG, IMECwith the collaboration of ST-I team are involved in validation of thermal-aware modeling framework. To de decided:Other partner contributes could be evaluated. By June 2012 first results are expected.