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Production

Production. Yield. Acceptance criteria. Test. PS & SPD LHCb Calo PRR – March 2004 – CERN. I. Yield. According to these results yield is about 85 %. II. Acceptance criteria (I). Possible scenario (using PMT load resistors of 470 ) :

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Production

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  1. Production • Yield. • Acceptance criteria. • Test. PS & SPD LHCb Calo PRR – March2004 –CERN

  2. I. Yield. • According to these results yield is about 85 %.

  3. II. Acceptance criteria (I). • Possible scenario (using PMT load resistors of 470): • Signal 0 – 25 ns about 76 % and tail 25 – 50 ns about 22 % • MIP signal 0 – 25 ns between 83 and 21 mV for PMT uniformity factor of 4 (gain is 1.1 mV/fC). • Noise 2 mV r.m.s. • SNR for MIP signal is between 40 and 10. • Resolution is given by the LSB of the internal DAC, LSB=3.2 mV seems to be enough to cover the offsets of about the 95% of the chips. • Resolution between 4 % and 16 %. • SNR can be increased if needed with larger PMT load resistors. • It is possible to compensate the PMT gain non-uniformities and the ASIC offsets tuning the input resistors. Offset: µ = -70  = 55 DAC: Offset = 0 LSB = 4 Units are in mV 143 µ+2.5 = 60 µ-2.5 = -200 1 MIP 83 max. - 63 LSB= -200 63 LSB= 200

  4. II. Acceptance criteria (II). • Defects are found in about 15% of the chips. • No special rejection criteria on offset is needed. • No rejection criteria on linearity or pile-up correction seems to be needed since all the chips that have been tested are within requirements. • A yield >80% is assumed • To equip 100 boards, 800 chips are needed. • To keep 20% of spare chips, a production of 1250 units is required

  5. III. Test. • The following points should be included in the test of the complete production: • Offset • Gain • Pile-up correction • Digital interface • A new VHDL code is under development to accelerate the test (it will include threshold scan algotiyhms).

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