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MIPS Datapath Implementation: A Comprehensive Overview

Explore the detailed architecture and methodology of MIPS datapath implementation, including key components, instruction sets, and execution flow. Gain insights into efficient single-cycle and multiple-cycle implementations. Understand the critical components like instruction memory, ALU, registers, and more.

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MIPS Datapath Implementation: A Comprehensive Overview

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  1. Topic 5:Processor Architecture Implementation Methodology \course\cpeg323-05F\Topic5-323.ppt

  2. Reading List • Slides: Topic5x • Henn & Patt: Chapter 5 • Other papers as assigned in class or homework \course\cpeg323-05F\Topic5-323.ppt

  3. ABET Outcomes • Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) • Ability to use the techniques, skills and modern engineering tools necessary for engineering practice • Knowledge of related topics in computer science discipline \course\cpeg323-05F\Topic5-323.ppt

  4. Outline • An overview • Datapath building blocks • Implementation of a simple (single-cycle) datapath • A multiple cycle implementation \course\cpeg323-05F\Topic5-323.ppt

  5. Overview • The basic instruction execution flow • Some conventions • 32 bit datapath • clocking strategy (edge-triggered) • We focus on a subset of MIPS • Memory-reference instructions: lw, sw • ALU ops: add, sub, and, or • Branch equal instructions (beq) and the jump instruction (J) \course\cpeg323-05F\Topic5-323.ppt

  6. Data Register # Registers Register # Register # Instruction PC ALU Address Data Memory Data Instruction memory An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them. \course\cpeg323-05F\Topic5-323.ppt

  7. Datapath Components • Common to all instructions: • Instruction memory • PC and its update • Datapath of R-R type instructions • ALU • Register set • Datapath of memory-reference instructions • ALU (for address calculation) • Register set • Sign extension unit • data memory • Datapath for a branch inst. (e.g. beq $1, $2, offset) • Sign extension + 2bit shifter • Reg • Adder • ALU (zero output) \course\cpeg323-05F\Topic5-323.ppt

  8. Instruction address PC Instruction ALU Sum Instruction memory Write a. Instruction memory b. Program counter c. Adder Two state elements are needed to store and access instructions, and an adder is needed to compute the next instruction address. \course\cpeg323-05F\Topic5-323.ppt

  9. Add 4 Read address PC Instruction Instruction memory A portion of the datapath used for fetching instructions and incrementing the program counter. \course\cpeg323-05F\Topic5-323.ppt

  10. Read register 1 Read data 1 ALU operation Register numbers Read register 2 Registers ALU result ALU Write register Read data 2 Write Data Data Write a. Registers b. ALU The two elements needed to implement R-format ALU operation are the register file and the ALU \course\cpeg323-05F\Topic5-323.ppt

  11. Read register 1 Read data 1 Read register 2 Zero Instruction ALU Registers ALU result Write register Read data 2 Write Data The datapath for R-type instruction \course\cpeg323-05F\Topic5-323.ppt

  12. Write Read address Read data Sign extend Write address Data memory Write Data Read 16 32 a. Data memory unit b. Sign-extension unit The two units needed to implement loads and stores are the data memory unit and the sign-extension unit, in addition to the register file and ALU \course\cpeg323-05F\Topic5-323.ppt

  13. Read register 1 Read data 1 Read address Zero Read register 2 ALU Instruction ALU result Read data Registers Write register Write address Data memory Read data 2 Write Data Write Data 16 32 Sign extend The datapath for a load or store that does a register access \course\cpeg323-05F\Topic5-323.ppt

  14. PC + 4 from instruction datapath Adder Branch target Sum Shift left 2 Read register 1 Instruction Read data 1 Read register 2 To branch control logic Registers ALU Zero Write register Read data 2 Write Data 16 32 Sign extend The datapath for a branch uses an ALU for evaluation of the branch condition and a separate adder for computing the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the I instruction (the branch displacement) shifted left 2 bits. \course\cpeg323-05F\Topic5-323.ppt

  15. A Simple (one-cycle) Datapath Implementation • One-cycle: • No resource can be used more than once by an instruction • If used more than once ==> duplicate it! • Sharing a resource by 2 or more instructions are done through multiplexing. \course\cpeg323-05F\Topic5-323.ppt

  16. Combining the datapaths for the memory instructions and the R-type instructions \course\cpeg323-05F\Topic5-323.ppt

  17. The instruction fetch portion of the datapath is appended to the datapath that handles memory and ALU instructions. \course\cpeg323-05F\Topic5-323.ppt

  18. The simple datapath for the MIPS architecture combines the elements required by different instruction classes. \course\cpeg323-05F\Topic5-323.ppt

  19. ALU operation a b Zero Result Overflow ALU CarryOut ALU Control The symbol commonly used to represent an ALU. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder. The control lines labeled ALUOperation . Their values and the ALU operation are found in the next figure. \course\cpeg323-05F\Topic5-323.ppt

  20. ALU Control cont’d The values of the three ALU Control lines and the corresponding ALU operations. ALU Control lines Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than \course\cpeg323-05F\Topic5-323.ppt

  21. This table shows how the ALU control bits are set depending on the ALUOp control bits and the different function codes for the R-type instruction. The opcode, listed in the first column, determines the setting of the ALUOp bits. All the encoding are shown in binary. Notice that when the ALUOp code is 00 or 01, the output fields do not depend on the function code field; in this case, we say that we “don’t care” about the value of the function code, and the function field is shown as XXXXXX. When the ALUOp value is 10, the function code is used to set the ALU control input. \course\cpeg323-05F\Topic5-323.ppt

  22. Instructions using ALU Load/store: address calculation - add Branch eq: subtract add/subtract R-type: and/or set-on-less-than need function code \course\cpeg323-05F\Topic5-323.ppt

  23. ALU Control Design The truth table for the three ALU control bits as a function of the ALUOp and function code field. Some don’t care entries have been added. For example, the ALUOp does not use the encoding 11, so the truth table can contain entries 1X, and X1 rather than 10 and 01.. \course\cpeg323-05F\Topic5-323.ppt

  24. ALUOp ALU control block ALUOp0 ALUOp1 Operation 2 F3 F2 F1 F0 Operation F (5-0) Operation 1 Operation 0 The ALU control block generates the three ALU control bits, based on the function code and ALUOp bits. \course\cpeg323-05F\Topic5-323.ppt

  25. Features of MIPS Instruction Format Field 0 rs rt rd shamt funct Bit positions 31-26 25-21 20-16 15-11 10-6 5-0 a. R-type instruction Field 35 or 43 rs rt address Bit positions 31-26 25-21 20-16 10-6 b. Load or store instruction Field 4 rs rt address Bit positions 31-26 25-21 20-16 15-0 c. branch instruction \course\cpeg323-05F\Topic5-323.ppt

  26. Features of MIPS Instruction Format cont’d • The op field, also called the opcode, is always contained in bits 31-26. We will refer to this field as Op[5-0]. • The two registers to be read are always specified by the rs and rt fields, at positions 25-21 and 20-16. This is true for the R-type instructions, branch equal, and for store. • The base register for load and store instructions is always in bit positions 25-21 (rs). • The 16-bit offset for branch equal, load, and store is always in positions 15-0. • The destination register is in one of two places. For a load it is in bit positions 20-16 (rt), while for an R-type instruction it is in bit positions 15-11 (rd). Thus, we will need to add a multiplex or to select which field of the instruction is used to indicate the register number to be written. \course\cpeg323-05F\Topic5-323.ppt

  27. PCSrc 0 M u x 1 ALU ALU result Add 4 Shift left 2 RegWrite Instruction(25-21) MeWrite Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Read address MemtoReg PC Instruction(20-16) Zero ALU result Instruction (31-0) Add Read address Write address Write data 0 M u x 1 0 M u x 1 Read data 1 M u x 0 Instructin memory Data memory Instruction(15-0) 32 16 Sign extend ALU control MemRead RegDst Instruction(5-0) ALUOp Instruction(15:11) The datapath with all necessary multiplexors and all control lines identified. \course\cpeg323-05F\Topic5-323.ppt

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