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Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors. Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock. Bias Analysis Approach. Assume an operation region (generally the saturation region) Use circuit analysis to find V GS Use V GS to calculate I D , and I D to find V DS

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Chapter 4 Field-Effect Transistors

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  1. Chapter 4Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock Microelectronic Circuit Design McGraw-Hill

  2. Bias Analysis Approach • Assume an operation region (generally the saturation region) • Use circuit analysis to find VGS • Use VGS to calculate ID, and ID to find VDS • Check validity of operation region assumptions • Change assumptions and analyze again if required. NOTE :An enhancement-mode device with VDS = VGS is always in saturation Microelectronic Circuit Design McGraw-Hill

  3. Four-Resistor and Two-Resistor Biasing • Provide excellent bias for transistors in discrete circuits. • Stabilize bias point with respect to device parameter and temperature variations using negative feedback. • Use single voltage source to supply both gate-bias voltage and drain current. • Generally used to bias transistors in saturation region. • Two-resistor biasing uses lesser components that four-resistor biasing and also isolates drain and gate terminals Microelectronic Circuit Design McGraw-Hill

  4. Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing) Problem: Find Q-pt (ID, VDS ,VGS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage.Find VGS and then use this to find ID. With ID, we can then calculate VDS. Microelectronic Circuit Design McGraw-Hill

  5. Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)(contd.) Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used. Since IG=0, Microelectronic Circuit Design McGraw-Hill

  6. Bias Analysis: Example 2 (Load Line Analysis) Problem: Find Q-pt (ID, VDS ,VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumption: Transistor is saturated, IG=IB=0 Analysis: For circuit values above, load line becomes Use this to find two points on the load line. Microelectronic Circuit Design McGraw-Hill

  7. Bias Analysis: Example 2 (Load Line Analysis)(contd.) @VDS=0, ID=100uA @ID=0, VDS=10V Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve. Check: The load line approach agrees with previous calculation.Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. Microelectronic Circuit Design McGraw-Hill

  8. Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation) Assumption: Transistor is saturated, IG=IB=0 Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage.Find VGS and then use this to find ID. With ID, we can then calculate VDS. Problem: Find Q-pt (ID, VDS ,VGS) of previous example, given =0.02 V-1. Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Microelectronic Circuit Design McGraw-Hill

  9. Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation) Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (54.5 mA, 4.55 V) with VGS= 3.00 V Discussion: The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including  effects in most circuits. Microelectronic Circuit Design McGraw-Hill

  10. Bias Analysis: Example 4 (Four-Resistor Biasing) Assumption: Transistor is saturated, IG=IB=0 Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage Problem: Find Q-pt (ID, VDS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Microelectronic Circuit Design McGraw-Hill

  11. Bias Analysis: Example 4 (Four-Resistor Biasing) Since VGS<VTNfor VGS= -2.71 V and MOSFET will be cut-off, and ID= 34.4 mA Also, Since IG=0, VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (34.4 mA, 6.08 V) with VGS= 2.66 V Microelectronic Circuit Design McGraw-Hill

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