Chapter 8 – Machine Instructions

1. Chapter 8 – Machine Instructions These are lecture notes to accompany the book SPARC Architecture, Assembly Language Programming, and C, by Richard P. Paul, 2nd edition, 2000. Updated Spring 2014 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

2. Decoding Instructions • SPARC Instructions are 32 bits long • Bits <31:30> specify the “op” field • These first 2 bits indicate how the other bits should be handled. op 31 30 29 0 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

3. Decoding Instructions • Instructions are classified according to “op” op 31 30 29 0 op Instruction class 00 Branch instructions 01 Call instructions 10 Format Three instructions 11 Format Three instructions Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

4. Format 1 Instructions • Call instruction • The displacement must be word aligned • Address is calculated by right shifting displacement 2 positions 01 30 bit displacement 31 30 29 0 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

5. Format 2 Instructions • branch 0 0 a cond op2 22 bit immediate 31 30 29 28 25 24 22 21 0 • sethi 0 0 rd 1 0 0 22 bit immediate 31 30 29 25 24 22 21 0 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

6. Branch Instructions • The branch is (or is not) taken based on the “cond” (condition) field. • op2 = 010 means integer condition code cond branch type 0000 never 0001 if equal to zero 0010 if less than or equal to zero 0011 if less than zero 0100 if less or equal, unsigned 0101 if carry set 0110 if negative 0111 if overflow is set cond branch type 1000 always 1001 if not equal to zero 1010 if greater than zero 1011 if greater than or equal to zero 1100 if greater, unsigned 1101 if carry is clear 1110 if positive 1111 if overflow is clear Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

7. Format 3 Instructions • 2 source registers 1 x rd op3 rs1 0 rs2 31 30 29 25 24 19 18 14 13 12 5 4 0 • Immediate constant 1 x rd op3 rs1 1 signed 13-bit # 31 30 29 25 24 19 18 14 13 12 5 4 0 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

8. Format Three Instructions • Not all possible bits patterns are used • op = 10 op3 Instruction 000000 add 000001 and 000010 or 000011 xor 000100 sub 000101 andn 000110 orn 000111 xnor 001000 addx op3 Instruction 111000 jumpl 111001 rett 111010 ticc 111011 iflush 111100 save 111101 restore 111110 <unused> 111111 <unused> See page 235 for a complete list Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

9. Format Three Instructions • Not all possible bits patterns are used • op = 11 op3 Instruction 000000 ld 000001 ldub 000010 lduh 000011 ldd 000100 st 000101 stb 000110 sth 000111 std 001000 <unused> See page 236 for a complete list Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

10. Register coding Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

11. Load/Store instructions • Load and Store instructions have two references – a register and memory location • rd field – refers to the register component • rs1 field – refers to register for memory address • rs2 field/immediate – refers to offset for memory address Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

12. Load/Store examples ldub [%o3 + %l2], %o1 stb %l0, [%o1 + %o2] stb %o5, [%o1 + 50] rd rs2 rs1 rd rs2 rs1 immediate rd rs1 Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C

13. Example • Decode the following commands: 0x9de3bfa0 0xd007bfec 0x92102004 0x90020009 0xd027bfec 0x81c7e008 0x81e80000 save %sp, -96, %sp ld [%fp-20], %o0 mov 4, %o1 add %o0, %o1, %o0 st %o0, [%fp-20] ret restore Richard P. Paul, SPARC Architecture, Assembly Language Programming, and C