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International Master of Science Program in System-on-Chip (SoC) Design at KTH SoC Masters

International Master of Science Program in System-on-Chip (SoC) Design at KTH SoC Masters. Axel Jantsch Royal Institute of Technology Electronic System Design Laboratory Email:axel@ele.kth.se. Background. The challenge. The challenge: example.

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International Master of Science Program in System-on-Chip (SoC) Design at KTH SoC Masters

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  1. International Master of Science Program inSystem-on-Chip (SoC) Design at KTHSoC Masters Axel Jantsch Royal Institute of Technology Electronic System Design Laboratory Email:axel@ele.kth.se

  2. Background

  3. The challenge

  4. The challenge: example • In year 2005 our students are launching a design project for I-Phone with the following properties: • Single chip phone, PDA, TV, mini-DVD recorder, GPS, and medical monitoring device inttegrated to a compact handheld device • On-chip RF (Bluetooth, GSM+, W-CDMA and local 4th generation wideband), optical I/F to home theater system • Clock internally at 2.8 GHz, externally 820 MHz, 300 MHz JTAG • 135 million gates, 256Mb embedded RAM (of which 144 Mb used by 3-D engine mainly for textures) • Single 1.5 V battery (AAA), 1 month standby, 4 hour DVD, 24 h web, 2 day phone • Full user and location awareness, build-in software agents for user adaptation and network adaptation (cognitive radio) • 4 Terabit all-electronic harddisk • What are the open issues? • System noise budgets (even for digital parts) • System interference of its own analog and RF functionality; deep submicron effects • Specification and design of functionality and performance characteristics • Verfication • Globalisation of the product design and industrial activities with multi-cultural and geographically distributed teams

  5. System-on-Chip int. M.Sc. program: SoC Masters www.ele.kth.se/SoC/

  6. Group A: Design of heterogeneous SoC architectures containing custom hardware, digital signal processors (DSP), microprocessors, and embedded software. Group B: Physical integration and implementation of heterogeneous blocks such as hardware, analog interfaces while optimizing power consumption, performance, cost, and noise. Group C: SoC design methodology issues such as specification and validation, integrating the separate design flows for tightly coupled hardware and software development and supporting CAD tools. Three Lines of Courses

  7. Courses • Course Credit units Quarter • Hardware modeling (C)4 1 • Embedded systems (A)5 1 • Digital circuit design (B)5 1-2 • Digital hardware organization (A) 4 2 • Design of fault-tolerant systems (A) 4 2 • SoC Architectures (A) 4 2 • Digital systems engineering (B) 5 3 • Design documentation & IPR issues (C) 4 3 • Anatomy of CAD tools for electronic design automation (C) 5 3

  8. Courses • System modeling (C) 5 3 • Electronic system packaging (B) 5 4 • Radio electronics (B) 5 4 • Low power analog & • mixed signal IC´s (B) 5 4 • System ASIC design (A) 5 4 • Special topics in SoC (C) 4 4 • Master's thesis (2nd year) (A-B-C) 20 1-2

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