Peter W Phillips Ashley Greenall Matt Warren Bruce Gallop Rick Shaw 08/03/2013

1. Peter W Phillips Ashley Greenall Matt Warren Bruce Gallop Rick Shaw 08/03/2013

2. Passive Probe Card Recall: ABCN25 Functional Test Bonded Chip Card & Common Driver “Driver” board was actually just a buffer and MUX, really driven by NI hardware

3. Recall: ABCN25 Wafer Test Digital Test Vectors supplied by Francis Anghinolfi as .vcf files • Block A CV • Block B CI W shunt • Block C CI M shunt1 • Block D CI M shunt2 DVM measurements • DAC linearity using ABCN internal MUX • Vout from internal LDO Analogue Tests • Two Point Gain • Two Point Trim Wafer A5GJ0HX

4. ABC130 Test Proposal Driver PCB SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC SAMTEC ABC130 “Baby” Sensor (optional) HV Standard Probe card ends in 0.1” pitch header: add mezzanine PCB to adapt to two SAMTEC headers. (RH header is used alone for hybrid R/0) Propose companion single chip PCB with identical SAMTEC pinouts. This takes one ABC130 and (optionally) a “baby” strip sensor

5. 100nF 100nF 100nF 100nF SCAN TEST Pads here PRELIMINARY Analogue MUX pads here ABC-130 Not to scale! Edge Sensor wired to A9, A10 ? Final Pad Frame is on hold pending better understanding of FE stability concerns => concentrate on Driver PCB for time being

6. What’s on the Driver PCB?(simplified) TO HSIO SAMTEC 50 SAMTEC 40 Spartan 3AN AD7998 Spartan initially programmed as “passive” SLVS buffer BUT can be programmed as HCC for hybrid & module tests ASIC POWER Unused for Hybrid test AD7998 MOLEX 12 SHUNT CONTROl BLOCK AD7998 TO DEVICE UNDER TEST Use both headers for ASIC test RH cable only for hybrid test SAMTEC 40 SAMTEC 40 Not to scale!

7. PRELIMINARY • PINOUTS • “COMMON” header • All SLVS • HCC monitoring lines • Power to (real) HCC • “ASIC” header • All CMOS • ASIC Power • DAC characterisation

8. What will be Tested? • Currents • Shunts and LDOs on and off • Digital Test Vectors • DAC characterisation • AnaMux and TestCom • SLVS / Termination check • ADC to measure HI and LO levels in steady state • Also checks probe contact  • Three Point Gain • Driver needs extra circuitry over that needed for hybrids • Address & Enable lines • ADCs for analogue measurements • Analogue switch and Shunt Control block • GND or control line

9. Same driver board as for ASIC test (but with different firmware) can be used to emulate HCC. This may possibly include ADCs. Can make smaller driver PCB better suited to module (stave) tests if required by HCC schedule.

10. ABC130 in SCTDAQ • ABC130 appears as a special input stream • HSIO decodes packets to a 64-bit aligned sequence • Send bit data to ABC on one of 4 streams • Recent addition is the option of a timed L0 • For “CAL+L1A”, but tested with BCR + L0 • 2 “ABC130s” in a chain have been tested • SCTDAQ sends commands • Mapping old to new • BCR -> BCR • Soft Reset -> L0IDReset (Aim is to know next L0) • L1 -> L0 + L1 + (R3) • keeps track of L0 since reset • each is a separate command to HSIO so asynchronous

11. N-Mask test (one “ABC130”) • Mask is set by bit • Readout interleaved • Also see R3 (ignored for time-being) • Using test mode (put mask into pipeline) • Here collected in 1BC mode, can also use 3BC

12. What’s next? • Driver Schematic under preparation by Rick • Details being fixed as this progresses • Hope to have something for discussion at Berlin • Then proceed to layout • Single Chip board and Probe Card • On hold until final pad frame released • Four power domains (two ins, two outs) + stability concerns => full custom probe card? • Firmware • Configure a second HSIO as a “mini-hybrid” • Use this to test firmware/software in detail