RD53 Analog IP blocks WG : developments and plans at CPPM

1. RD53 Analog IP blocks WG :developments and plans at CPPM M. Barbero, L. Gallin Martel (LPSC), Dzahini (LPSC), D. Fougeron, R. Gaglione (LAPP), F. Gensolen, S. Godiot, M. Menouni, P. Pangaud, F. Rarbi (LPSC), A. Wang, A. Rozanov CPPM - Aix-Marseille Université

2. Pixel configuration memory • Previous tests on the LBL chip : • Good results in term of tolerance to SEU • Design based on standard cells from ARM library • Some issues with dose effects • A new design is now under development • Design tolerant to a total dose of 1000 MRad • Minimize the effect of glitches • Test of new structures (based on Hamming code …) to reduce the memory cell area Datain Majority Logic Latch1 sel Latch2 t Latch3 2t IP Blocks 65 nm design

3. Generic ADC for monitoring • General purpose ADC • Inputs are slow variation signals : • Temperature, leakage current … • Power supply = 1.2 V • Sampling rate: (10 -100) ksample/s • Architecture : Successive Approximation Register (SAR) • Precision : 12 bit (LSB ~ 250 µV) • DC accuracy : • Integral linearity error : +/- 1 bit • Differential linearity error +/- 0.5 bit • Operating input voltage : 0-Vref • Conversion time : 12-14 clock cycles • Tolerance to a TID of 1000 Mrad • Need of a very stable Voltage Reference out 12 bit SAR ADC Analog MUX inputs Vin status clk start enable select IP Blocks 65 nm design

4. Bandgap reference • Bandgap Reference for general purpose provide voltage reference for : • Biasing, DAC, ADC … • Power supply = 1.2 V • 2 Voltages : to be defined (0.8 V? and 0.6 V?) • Temperature : from -50 °C to 120 °C • Temperature coefficient : 400 ppm/°C max • Voltage coefficient : TBD • Start up circuit • CLoad MAX = 20pF and RLoad = 10 MOhm • Noise < 20 µV RMS • Radiation hard : 1000 Mrad • Base current compensation (others structures) • DTMOS structure • Avoid trimming ? M2 M1 M3 N3 VOUT N4 RB1 RA1 R3 R1 N2 N1 D1 =M*D2 RA2 D2 RB2 IP Blocks 65 nm design

5. Multi Purpose Op Amplifier • General purpose operational amplifier • Power supply = 1.2 V • Rail to rail input and output • High output driving capability • CLOAD MAX = 10 pF • DC gain > 70 dB • Gain-Bandwidth product GBWP > 10 MHz • Slew rate : TBD • Phase margin = 70° • CMMR : TBD • PSSR :TBD • Irradiation tolerance : 1000 Mrad Vdda Vbn inn out MPOA inp en Gnda IP Blocks 65 nm design

6. Temperature Sensor • Precision : +/- 1 °C • Functional temperature range -40 to +60 °C • Sensitivity better than 0.6 mV/°C • Radiation tolerance : 1000 MRad • Correction of the irradiation effect • Output value digitized by the GADC Vbn Vdda out en TempSens Gnda IP Blocks 65 nm design

7. Conclusion • Deliverables • Virtuoso OA database : Schematic, symbol and layout views • Post layout netlist (RC parasitics) • Documentation including the main DC levels, simulations et test results • Next submission • The design of some IP blocks is in progress • We would like to submit some design blocks at the beginning of 2014 • We are looking for partners to share a MPW IP Blocks 65 nm design