Life Test Effects on the Aeroflex ViaLink™ FPGA

1. Life Test Effects on the Aeroflex ViaLink™ FPGA Ronald Lake Aeroflex Colorado Springs Lake

2. Purpose of Investigation • Industry is currently evaluating long term reliability of antifuse products • Aeroflex is proactively reviewing long term reliability of RadHard Eclipse ViaLink™ products • Burn-in • Low Temperature Operating Life (LTOL) • High Temperature Operating Life (HTOL) • Accelerated Voltage • Monitor Lake

3. Techniques for Long Term Reliability Analysis • Accelerated burn-in: unprogrammed devices • Chamber temperature: 125ºC • Stress pattern: dynamic, 1MHz, production unprogrammed device test • Duration: 16 hours • Stress voltages: 4.1V I/O; 3.2V core • Test: room temp unprogrammed electrical test, read and record • Low temperature operating life (LTOL): programmed devices • Chamber temperature: -65ºC • Stress pattern: dynamic, 1MHz, 10K vectors, high toggle rate • Duration: 500 hours (read point at 24hrs, 168hrs) • Stress voltages: 3.3V I/O, 2.75V core • Test: 3 temp electrical test, read and record data Lake

4. Techniques for Long Term Reliability Analysis • High temperature operating life (HTOL): programmed devices • Accelerated HTOL • Chamber temperature: 125ºC • Stress pattern: dynamic, 10K vectors, high toggle rate • Duration: 500 hours (read point at 96hrs) • Stress voltages: 4.1V I/O, 3.2V core • Test: 3 temp electrical test, read and record data • HTOL monitor - replicates customer use conditions • Chamber temperature: 125ºC • Stress pattern: dynamic, 10K vectors, high toggle rate • Duration: 1000 hours (read point at 500hrs) • Stress voltages: 3.3V I/O, 2.5V core • Test: 3 temp electrical test, read and record data Lake

5. Stress Voltage Margin • Operating voltage (functional operation) • 2.7 V core • 3.6 V I/O • Absolute Maximum • 3.6 V Core • 4.6 V I/O • Aeroflex Accelerated Voltage Stress Results • QL6325 used for evaluation (in plastic pkg) • 4.7 V Core (pass ET) • 4.9 V Core (Fails ET) • 5.5 V I/O (pass ET) • 6.0 V I/O (Fails ET) • No Auto Programming of ViaLinks Detected • Un-programmed Devices used for this evaluation Lake

6. Reliability Design for Life Test Effects Lake

7. Reliability Design for ViaLink™ Lifetest • Goal: Verify long term reliability of programmed and un-programmed vialinks with HTOL and LTOL tests • Design • Create worst case design, beyond customer’s ability • Use all FPGA logic, memory and I/O resources • Use all wiring types, with associated ViaLinks™ • Worst case design constraints • Force fan-out = 16 (user restricted to fan-out=10) • Force fixed placement to drive long interconnects • Force use of worst case ViaLinks™ with fixed placement • Disable automatic buffering • Use design structures which may be toggled efficiently during life test Lake

8. Resource Utilization for Reliability Design Utilized cells (preplacement) 1533 of 1536 (99.8) Utilized cells (postplacement) 1514 of 1536 (98.6) Utilized Logic cell Frags (preplacement) 7195 of 9216 (78.1) Utilized Logic cell Frags (postplacement) 7195 of 9216 (78.1) Utilized Fragment A 1164 Utilized Fragment F 1302 Utilized Fragment O 1393 Utilized Fragment N 1056 IO control cells 16 of 16 (100.0) Clock only cells 9 of 9 (100.0) Bi directional cells 99 of 99 (100.0) RAM cells 24 of 24 (100.0) PLL cells 0 of 4 (0.0) Flip-Flop of IO cells 70 of 316 (22.2) 1st Flip-Flop of Logic cells 1097 of 1536 (71.4) 2nd Flip-Flop of Logic cells 1183 of 1536 (77.0) Routing resources 64210 of 119431 (53.8) ViaLink resources 57098 of 3213992 (1.8) Lake

9. Reliability Design Utilization With Customer Design Flow Utilized cells (preplacement) 1533 of 1536 (99.8) Utilized cells (postplacement) 1536 of 1536 (100.0) Utilized Logic cell Frags (preplacement) 8033 of 9216 (87.2) Utilized Logic cell Frags (postplacement) 8288 of 9216 (89.9) Utilized Fragment A 1536 Utilized Fragment F 1534 Utilized Fragment O 1447 Utilized Fragment N 1491 IO control cells 16 of 16 (100.0) Clock only cells 9 of 9 (100.0) Bi directional cells 99 of 99 (100.0) RAM cells 24 of 24 (100.0) PLL cells 0 of 4 (0.0) Flip-Flop of IO cells 70 of 316 (22.2) 1st Flip-Flop of Logic cells 1097 of 1536 (71.4) 2nd Flip-Flop of Logic cells 1183 of 1536 (77.0) Routing resources 65777 of 119431 (55.1) ViaLink resources 57520 of 3213992 (1.8) Lake

10. Reliability Design: Shift Register Details Lake

11. Reliability Design: Combinatorial Blocks Detail Lake

12. Reliability Design: Fixed Worst Case Placement Constraints Lake

13. Reliability Design: Short Path Placement Lake

14. Reliability Design: Combinatorial Fan-out Lake

15. Reliability Design: Worst Case Fan-out Lake

16. Reliability Design: LTOL / HTOL I/O Overshoot and Undershoot Lake

17. Reliability Design: Expanded View LTOL / HTOL I/O Overshoot Lake

18. LTOL Current Deltas Current Measurements for HTOL / LTOL Material Lake

19. Summary • Worst case design created to evaluate long term ViaLink™ reliability • Programmed and un-programmed ViaLink’s™ evaluated through low temperature operating life (LTOL) and accelerated high temperature operating life (HTOL) • Data to date shows no ViaLink™ damage during lifetest • No functional failures • No increase in quiescent or active current Lake