Introduction to CPLD/FPGA Technology, Devices and Tools

1. Introduction to CPLD/FPGATechnology, Devices and Tools Theerayod Wiangtong Electronic Department Mahanakorn University of Technology

2. Programmable Logic CPLD FPGA Architecture: Basic & Advance Examples Features Vendors and Devices Design Tools Outline

3. World of Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA

4. ASIC • ASIC: Application SpecificIntegrated Circuit • Designs must be sent for expensive and time consuming fabrication in semiconductor foundry • Designed all the way from behavioral description to physical layout

5. CPLD/FPGA • CPLD: Complex Programmable Logic Device • FPGA: Field Programmable Gate Array • Small development overhead • No NRE (non-recurring engineering) costs • Quick time to market • No minimum quantity order • Reprogrammable

6. Which Way to Go? Off-the-shelf High performance Low development cost Low power Short time to market Low cost in high volumes Reconfigurability ASICs CPLD/FPGAs

7. Other Advantages • Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower • Mistakes not detected at design time have large impact on development time and cost • FPGAs are perfect for rapid prototyping of digital circuits • Easy upgrades like in case of software • Unique applications • Reconfigurable computing

8. Programmable LogicCPLD/FPGA

9. Programmable Logic • Programmable digital integrated circuit • Standard off-the-shelf parts • Desired functionality is implemented by configuring on-chip logic blocks and interconnections • Types of programmable logic: • Complex PLDs (CPLD) • Field programmable Gate Arrays (FPGA)

10. A B C AND plane PLD - Sum of Products Programmable AND array followed by fixed fan-in OR gates Programmable switch or fuse

11. PLD - Macrocell Can implement combinational or sequential logic Select B A C Enable Flip-flop MUX D Q Clock AND plane

12. I/O Block PLD Block PLD Block I/O Block Interconnection Matrix Interconnection Matrix I/O Block PLD Block PLD Block I/O Block CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip

13. CPLD Example - Altera MAX7000 EPM7000 Series Block Diagram

14. CPLD Example - Altera MAX7000 EPM7000 Series Device Macrocell

15. FPGA Architecture

16. FPGA building blocks: Programmable logic blocksImplement combinatorial and sequential logic Programmable interconnectWires to connect inputs and outputs to logic blocks Programmable I/O blocksSpecial logic blocks at the periphery of device for external connections Logic block Interconnection switches I/O I/O I/O I/O FPGA - Generic Structure

17. Select Out LUT A B C D D Q Clock FPGA – Basic Logic Element • LUT to implement combinatorial logic • Register for sequential circuits • Additional logic (not shown): • Carry logic for arithmetic functions • Expansion logic for functions requiring more than 4 inputs

18. LUT A B Z A C D B Z C D Look-Up Tables (LUT) • Look-up table with N-inputs can be used to implement any combinatorial function of N inputs • LUT is programmed with the truth-table LUT implementation Truth-table Gate implementation

19. X1 X2 0/1 0/1 0/1 0/1 F 0/1 0/1 0/1 0/1 X3 LUT Implementation • Example: 3-input LUT • Based on multiplexers (pass transistors) • LUT entries stored in configuration memory cells Configuration memory cells

20. LE LE LE Switch Matrix Switch Matrix LE LE LE Programmable Interconnect • Interconnect hierarchy (not shown) • Fast local interconnect • Horizontal and vertical lines of various lengths

21. 6 pass transistors per switch matrix interconnect point Pass transistors act as programmable switches Pass transistor gates are driven by configuration memory cells Switch Matrix Operation After Programming Before Programming

22. Configuration Storage Elements • Static Random Access Memory (SRAM) • each switch is a pass transistor controlled by the state of an SRAM bit • FPGA needs to be configured at power-on • Flash Erasable Programmable ROM (Flash) • each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program • reprogrammable, even in-circuit • Fusible Links (“Antifuse”) • Forms a forms a low resistance path when electrically programmed • one-time programmable in special programming machine • radiation tolerant

23. FPGA Technology Roadmap

24. Special Features • Clock management • PLL,DLL • Eliminate clock skew between external clock input and on-chip clock • Low-skew global clock distribution network • Embedded memory blocks • Support for various interface standards • High-speed serial I/Os • Embedded processor cores • DSP blocks

25. Xilinx Virtex-II/Virtex-4: Feature-packed high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs Altera Stratix/Stratix-II High-performance SRAM-based FPGAs Cyclone/Cyclone-II Low-cost feature reduced version for cost-critical applications MAX3000/7000 CPLDs MAX-II: Flash-based FPGA Actel Anti-fuse based FPGAs Radiation tolerant Flash-based FPGAs Lattice Flash-based FPGAs CPLDs (EEPROM) QuickLogic ViaLink-based FPGAs FPGA Vendors & Device Families

26. State of the Art in FPGAs • 90 nm process on 300 mm wafers • Lower cost per function (LUT + register) • Smaller and faster transistors: Higher speed • System speed up to 500 MHz • Mainly through smart interconnects, clock management, dedicated circuits, flexible I/O. • Integrated transceivers running at 10 Gigabits/sec • More Logic and Better Features: • >100,000 LUTs & flip-flops • >200 embedded RAMs, and same number 18 x 18 multipliers • 1156 pins (balls) with >800 GP I/O • 50 I/O standards, incl. LVDS with internal termination • 16 low-skew global clock lines • Multiple clock management circuits • On-chip microprocessor(s) and multi-Gbps transceivers

27. Xilinx Virtex-4 90nm process Up to 960 I/Os >200000 logic cells Up to 552 18kb block RAMs (~10Mb RAM) 192 DSP slices (18x18 multiplier-accumulator) 20 digital clock managers (DCM) 24 high-speed serial transceivers (622Mb/s to 11.1Gb/s) Up to four PowerPC 405 cores Altera Stratix-II 90nm process Up to 1170 I/Os 179000 logic elements 9.6Mb embedded RAM 96 DSP blocks: 380 18x18 multipliers 12 PLLs Serial I/O up to 1Gb/s No hard processor cores Latest Devices: Capacity & Features

28. ALTERA

29. Device Families & Tools

30. Device Roadmap

31. Technology

32. Logic Density

33. Pricing Roadmap

34. FLEX10K Basic Architecture

35. Logic Array Block: FLEX10K

36. Logic Element of FLEX10K

37. Advance Altera Architecture

38. Stratix Device

39. Stratix Device Family

40. Altera: Embedded DSP Blocks • Two DSP Block columns per device • Number varies by height of column • Can implement: • Eight 9x9 multipliers • Four 18x18 multipliers • One 36x36 multiplier • Contains adder/subtractor/accumulator • Registered inputs can become shift register

41. Altera: Embedded DSP Block

42. Embedded RAM Dual-Port RAM • M512 – 512 x 1 • M4K – 4096 x 1 • M-RAM – 64K x 8

43. Embedded RAM Block

44. ALTERA High Speed I/O

45. Embedded Processor • Soft Processor: NIOS 32bit @150MHz • Hard Processor: ARM922T 32bit RISC @200 MHz (Excalibur device) • Additional features • Communication Controller • Integrated MMU (Memory Management Unit) • High-Speed Memory Interface • C-Level Simulation • Multi-Processor Support

46. NIOS II Family

47. Max II Device

48. Xilinx

49. Product Overview High Performance High Density High Volume Low Cost CPLD Rom-based Low Power Low Cost

50. Xilinx FPGA Families • Old families • XC3000, XC4000, XC5200 • Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. • High-performance families • Virtex (0.22µm) • Virtex-E, Virtex-EM (0.18µm) • Virtex-II, Virtex-II PRO (0.13µm) • Low Cost Family • Spartan/XL – derived from XC4000 • Spartan-II – derived from Virtex • Spartan-IIE – derived from Virtex-E • Spartan-3