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Pipeline Hazards Summary

Pipeline Hazards Summary. Summary. Forwarding Case Summary. Floating point Pipeline (Multi-cycle pipeline). Integer pipeline all ALU operations take one cycle Floating point operation takes multiple cycles to execute Use same pipeline with multiple floating point execution unit

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Pipeline Hazards Summary

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  1. Pipeline Hazards Summary

  2. Summary

  3. Forwarding Case Summary

  4. Floating point Pipeline (Multi-cycle pipeline) • Integer pipeline all ALU operations take one cycle • Floating point operation takes multiple cycles to execute Use same pipeline with multiple floating point execution unit Repeat the EXE stage until operation completes

  5. Multi-cycle Execution

  6. Multi-cycle Pipeline

  7. Hazard Detection • Because unequal functional unit times Adds the possibility of WAR and RAW hazards • Contention for writes Floating point LD and operation can contend for WB Only allow one instruction to enter memory from EXE stage • WAR hazards: not a problem if all instruction are executed in oder • WAW hazard: possible because of out of order completion Example: DIVF F0,F2,F4 SUBF F0,F8,F10 Since divides finishes last value in F0 is result of divide Solution: Delay issue of second inst. until first is done Do not write result of first inst. WAW hazard is rare choose easiest

  8. Handling interrupt • Must shut down pipeline and flush pipeline all instructions after interrupting instruction are removed all instruction before interrupting instruction are completed • Load instruction from interrupt handler. • Repeat execution from the instruction that caused interrupt • Precise interrupt: handle interrupt in the order they occur (1) F D X M W interrupt in MEM stage (2) F D X M W interrupt in EXE stage (3) F D X M W interrupt in F stage Which interrupt is seen first? If you handle interrupt once they occur 3 is seen first then 2 and 1? Solution post interrupt in a vector then at WB stage of each instruction check vector and handle them in the order of instructions. • Imprecise interrupt: Handle them in order they occur not recommended • Floating point operations complicates interrupt handling mechanism

  9. Motorola G4e

  10. Intel Pentium 4

  11. IBM PowerPC 970

  12. Pipelined processors divide execution in multiple steps However pipeline hazards reduce performance Structural, data, and control hazard Data forwarding helps resolve data hazards But all hazards cannot be resolved Some data hazards require bubble or noop insertion Effects of control hazard reduced by branch prediction Predict always taken, delayed slots, branch prediction table Structural hazards are resolved by duplicating resources Time to execute n instructions depends on # of stages (k) # of control hazard and penalty of each step # of data hazards and penalty for each Time = n + k - 1 + (load hazard penalty) + (branch penalty) Load hazard penalty is 1 or 0 cycle Depending on data use with forwarding Branch penalty is 3, 2, 1, or zero cycles depending on scheme Important facts to remember

  13. Design and performance issues with pipelining • Pipelined processors are not EASY to design • Technology affect implementation • Instruction set design affect the performance • i.e., beq, bne • More stages do not lead to higher performance!

  14. Pipeline Summary • Pipelining does not improve latency, but does improve throughput

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