Leakage Power Reduction Techniques

1. Leakage Power Reduction Techniques Yuanlin Lu ECE Dept. Auburn University ELEC 6970

2. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

3. I2, I5, I6 and are off-state leakage mechanisms; I1 and I3 occur in both ON and OFF states; I4 can occur in the off state, but more typically occurs during the transistor bias states in transition. I1 - the reverse-bias pn junction leakage; I2 - the subthreshold leakage; weak inversion conduction current between source and drain in an MOS transistor occurs when gate voltage is below Vth. I3 - the oxide tunneling current; due to the low oxide thickness and the high electric field; I4 - the gate current due to hot-carrier injection; I5 - the GIDL (Gate-Induced Drain Leakage); due to high field effect in the drain junction; I6 - the channel punchthrough current; due to the proximity of the depletion regions of the drain and the source. Transistor Leakage Mechanisms ELEC 6970

4. Subthreshold Leakage current u0 is the zero bias electron mobility, n is the subthreshold slope coefficient. To decrease Subthreshold current • Cox = εox/Tox Determined by foundry • Vgs & Vds Vdd  dual power supply • Vth  dual-Vth, Multi-Vth, Variable Vth • W or L  gate sizing • Temperature ( VT = KT/q) ELEC 6970

5. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

6. Leakage & Delay • Increasing Vth can decrease Isub exponentially • But, gate delay increase at the same time where α models short channel effects (1.3) • When using Vth changing techniques, must consider the tradeoff between leakage reduction and performance reduction ELEC 6970

7. MTCMOS (Multi-Threshold CMOS) ELEC 6970

8. Advantage - Circuit can be modified easily Disadvantages - Affect delay, area - Can only reduce leakage power in standby mode - Not suitable for sequential circuit MTCMOS (cont.) ELEC 6970

9. VTMOS (Variable Threshold CMOS) • Using body effect, change Vth • In active mode, a zero body bias • In standby mode, a deeper reverse body bias, Vth increase • Can only reduce leakage power in standby mode • Vth0 - zero-substrate-bias value for Vth • r - body effect parameter • 2ФF- surface potential parameter • η - Drain-induced barrier lowering (DIBL) coefficient (0.02-0.1) ELEC 6970

10. VTMOS (cont.) ELEC 6970

11. Dual Threshold CMOS • To maintain performance, all gates on the critical path are assigned low Vth • Part of the gates on the non-critical paths are assigned high Vth • Disadvantage: Circuit structure sensitive • Advantage: Can reduce leakage power in both standby mode and active mode ! ELEC 6970

12. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

13. Dual Power Supply Voltages • Vdd Isub  gate delay • Assign Low Vdd to the gates on the non-critical path, to decrease leakage power • Assign High Vdd to the gates on the critical path, to maintain performance ELEC 6970

14. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

15. Serious connected ‘off’ Transistors (Transistor Stacking) can reduce leakage current greatly When M1 and M2 are turned off, Vm at the intermediate node is positive due to small drain current. Vgs1 < 0, reduce the subthreshold current substantially. Vbs1 < 0, increase Vth1 (larger body effect) and thus reducing the subthreshold leakage. Vds1 decrease, increase Vth1 Vds2 decrease, increase Vth2 Transistor Stacking Vm ELEC 6970

16. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

17. Different Input vector, different leakage current. 00: p1 & p2 on, n1 & n2 off. Ileak00 = In1 + In2 = 2 * Ileak 01: n1 off. n2 is on and can be treated as shorted, so leakage current of n1 is ignored. p1 is on and p2 is off. Ileak01 = Ip2 = Ileak 10: the same as the ‘01’ Ileak10 = Ip1 = Ileak 11: n1 & n2 on. p1 & p2 off. Due to the stacking effect, Ileak 11 < Ileak So, when the input vector is ‘00’, the NOR gate has the maximal leakage current. When the input vector is ‘11’, the NOR gate has the minimum leakage current. Leakage Dependence on the Input Vector ELEC 6970

18. Optimal Input Vectors Selection • There must be optimal primary input vectors which lead to the minimum leakage power in the standby mode. • For smaller ciruits - Exhaustive Search • For larger circuits - Random Search - Genetic algorithm ( exploit historical information to speculate on new search points with expected improved performance to find a near-optimal solution ) ELEC 6970

19. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

20. Dual Threshold CMOS • To maintain performance, all gates on the critical path are assigned low Vth • Part of the gates on the non-critical paths are assigned high Vth, to avoid the change from non-critical path to critical path. • Disadvantage: Circuit structure sensitive • Advantage: Can reduce leakage power in both standby mode and active mode ! ELEC 6970

21. Using ILP (Integer Linear Programming) to Reduce Leakage Power • In dual-threshold CMOS process • Firstly, assign all gates low Vth • Use ILP model 1 to find the delay of the critical path (Tc) • Use ILP model 2 to find the optimal Vth assignment as well as the leakage reduction of all gates without increasing Tc • Further reduce leakage power by increasing Tc ELEC 6970

22. ILP • Raja et al. [16] proposed a technique to reduce dynamic glitch power by a reduced constraint set linear program. • We modify their formulation into an integer linear program (ILP) to reduce leakage power. • ILP is a mixed ( integer value and continuous values combined together) linear programming ELEC 6970

23. ILP -Variables Each gate has two variables. • Ti:the latest time at which the output of gate i can produce an event after the occurrence of an input event at primary inputs of the circuit. Continuous value • Xi:the assignment of low or high Vth to gate i; Xi is an integerwhich can only be 0 or 1. 1  gate i is assigned low Vth; 0  gate i is assigned high Vth. ELEC 6970

24. ILP - objective function objective function - minimize the sum of all gates leakage currents, which is given by • ILi is the leakage current of gate i with low Vth; • IHiis the leakage current of gate i with high Vth; • Each gate’s leakage current can be either ILi or IHi; • Using SPICE simulation results, we constructed a leakage current look up table, which is indexed by the gate type and the input vector. ELEC 6970

25. ILP - Constraints • Constraints for each gate (1) gate j ‘s output is gate i ‘s fan in (2) • Max delay constraints for primary outputs (PO) (3) Tmax can be spec. or the delay of the critical path ELEC 6970

26. ILP – Constraints 1 • assume all primary input (PI) signals on the left arrive at the same time. • For gate 2, constraints can be given by ELEC 6970

27. ILP – Constraints 1 (cont.) • DHi is the delay of gate i with high Vth; • DLi is the delay of gate i with low Vth. • A second look-up table is constructed and specifies the delay for given gate type and fanout number. ELEC 6970

28. ILP – Constraints 3 • Tmaxcan be spec. or the delay of the critical path (Tc). • To find Tc, we change constraints 2 to a equation, which means all gates are assigned low Vth. • The maximum Ti given by AMPL CPLEX, is equal to Tc. • If we replace Tmaxwith Tc, the real objection function becomes minimize leakage power without sacrificing any performance. ELEC 6970

29. If we gradually increase Tmax from the smallest value Tc, more leakage power can be reduced, because more gates on the non-critical path can be assigned high Vth. But, the reduction trend becomes slower. When Tmax = (130%) Tc, the reduction is saturated, because almost all the gates are assigned high Vth, and there is no more optimization space. The maximum leakage reduction can be 98%. Tradeoff between Leakage and Performance ILP – Constraints 3 (cont.) ELEC 6970

30. Results-Leakage Reduction ELEC 6970

31. Results-Dynamic & Leakage Comparison • VT (thermal voltage, kT/q) and Vth both depend on the temperature, so, leakage current also strongly depends on the temperature. • Spice simulation shows that for a 2-input NAND gate - with low Vth, Isub @ 90ºC = 10 * Isub @ 27ºC - with high Vth, Isub @ 90ºC = 20 * Isub @ 27ºC • To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage power @ 90ºC. ELEC 6970

32. Results-Dynamic & Leakage Comparison (cont.) • Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by • We apply 1000 random test vectors at PIs with the test period equal to (120%)Tc, and calculate the total transition No. in the circuit. ELEC 6970

33. Results-Dynamic & Leakage Comparison (cont. 2) ELEC 6970

34. Outline • Transistor Leakage Mechanisms • Leakage Reduction techniques - Mutli-, dual-, Variable Vth - Dual Power Supply - Transistor Sizing - Transistor Stacking - Optimal Input Vector Selection • Proposed Technique - Using ILP to Minimize leakage - Extend ILP to Minimize leakage and Glitch Power together ELEC 6970

35. Fig 1. A circuit with potential glitches Fig 2. Inserting buffers in the circuit of Figure 1 to balance the path delays to eliminate all glitches. Extend ILP to Minimize leakage and Glitch Power together Fig 3. Hazard filter effect of high Vth gates. • Three black gates are assigned high Vth. • Their delays increase accordingly. • Only two buffers are needed to eliminate all glitches due to the increased gate delay of high Vth gates. • This hazard filter effect is another advantage of dual-Vth reassignment. ELEC 6970

36. Extend ILP to Minimize leakage and Glitch Power together (cont.) • The inserted buffers for eliminating glitches consume additional leakage power, so, we may assign high Vth to them. • Most of the delay buffers are on non-critical paths and can be assigned high Vth. • For a larger circuit, the power saving due to hazard filtering would be significant while power increase due to delay buffers will be small ELEC 6970

37. Future Work • Using ILP to minimize leakage and dynamic power simultaneously. • Consider transistor sizing to reduce dynamic switching power and leakage power simultaneously. ELEC 6970

38. Thank You All !