1 / 18

Leakage Reduction in SRAM Utilizing Power Gating

Leakage Reduction in SRAM Utilizing Power Gating. Kyle Craig Yousef Shakhsheer. Objectives. To implement a leakage reduction energy standby mode that maintains state for SRAM, utilizing headers and footers. Current power-gating methods can cause bit cells to lose state. BC. Proposed Method.

karlyn
Download Presentation

Leakage Reduction in SRAM Utilizing Power Gating

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Leakage Reduction in SRAMUtilizing Power Gating Kyle Craig Yousef Shakhsheer

  2. Objectives To implement a leakage reduction energy standby mode that maintains state for SRAM, utilizing headers and footers. Current power-gating methods can cause bit cells to lose state.

  3. BC Proposed Method • Add headers/footers to SRAM bitcells/columns • Put the these bitcells/colums into sleep mode • All headers/footers turned off • Ability to maintain data in the cell, and save energy .

  4. Approach • Tested settling voltage • Figured out DRV • Assumed virtual VSS values and calculated the min VDD needed • Static Noise Margins (butterfly plots) • Test for functionality • Sensing Circuit

  5. Settling Voltage VDDv 1BC VDDv/VSSv 64BC VSSv 1BC

  6. Settling Voltage TT SS

  7. Settling Voltage Header/Footers min sized, 4096 shared BC

  8. DRV/Butterfly

  9. Test for Functionality • Normal Operation • Transitioning

  10. Sensing Circuit v1 Very Long ~5X min L Very Wide ~7X min W

  11. Sensing Circuit • Why Large W and L? • Need to make left NMOS (VSSv) stronger than the right NMOS • Gate voltage of VSSv will always be less than VDDv • Large width compensates for lower gate voltage. • Sizing can be tweaked to change the ΔV that it triggers on.

  12. VDDv VSSv Out

  13. Enable Out VDDv VSSv Enable Sensing Circuit v2

  14. Sensing Circuit • Enable is clocked • Output and Enable are NANDed together • Produced an overall out of 0 when it fires for a period of time

  15. VDDv VSSv NAND Out

  16. Sensing Circuit v1 vs v2 • V1 • Less complicated to control • Lower area • Limited sensing scope • More Energy • V2 • Lower Energy • Can handle wider scope of sensing since it is reset by the keeper PMOS

  17. Results Compare to 62 pJ!

More Related