Particles and Fields Package (PFP) SWEA Pre-CDR Peer Review

1. Particles and Fields Package (PFP) SWEA Pre-CDR Peer Review Ellen Taylor Space Science Laboratory, UCB

2. Outline • Overview (Block Diagram) • Requirements • Interfaces • Digital Board EM Status • LVPS Board EM Status • Resources • Schedule and Parts Status

3. CESR / UCB-SSL Collaboration SSL, Berkeley • Pedestal • Digital / FPGA • LVPS (same as for STEREO SWEA) IRAP/CESR, Toulouse • Analyzer • MCP • Anode • HVPS

4. SWEA Electrical Team – SSL • David L. Mitchell (Instrument Lead) • Ellen Taylor (Digital Electronics) • Dorothy Gordon (FPGA) • Peter Harvey (FSW [PFDPU]) • Peter Berg, Selda Heavner (Power Supplies) • Dave Curtis (Interfaces) • Tim Quinn (GSE) • Jorg Fischer (QA and Parts Lead)

5. SWEA Electrical Block Diagram UCB IRAP/CESR

6. SWEA Electrical Requirements MAVEN-PF-SWEA-002 SWEA Instrument Specification Functional and Performance Requirements Resource Allocations (board size, power budget) Environmental Requirements (thermal, vibration, radiation) MAVEN-PF-QA-002 UCB Mission Assurance Implementation Plan Parts Level Burn-In Derating MAVEN-PF-SYS-003 Power Converter Requirements Power voltages, current, ripple, transients MAVEN-SWEA-012 FPGA Specification PFDPU CLK/TLM/CMD Interface HV Enable (RAW and MCP) and DAC Control (Sweep and Fixed) Operational Heater Control Pre-amp Input, Test Pulser Output Housekeeping and Memory (external SRAM) I/F

7. SWEA Digital Board Interfaces MAVEN-PF-SWEA-001 CESR to SSL ICD Preamp Pulse Characteristics Test Pulser Frequencies HV Enable and Converter Synch DAC Control Voltages Sweep Waveforms Analog Housekeeping Connector Pin-out MAVEN-PF-SYS-004 PFDPU ICD PFDPU Serial I/F description (CMD/CLK/DATA) Power Interface (28V/RTN) MAVEN-PF-SYS-013 Harness Connector Pin-outs MAVEN-PF-SYS-003 Power Req. Power I/F (voltages, current, characteristics) MAV-RQ-09-0015 Particle and Fields to Spacecraft ICD Heater, Thermister and Cover Actuator Interface

8. Heritage and Design Similarities MAVEN SWEA digital board has direct heritage from STEREO SWEA: Minor interface changes (separate connector to SC for temp sensor, heater and actuator, external PFDPU connector) Changed interface logic to 3.3V from 5V (added translators 54ACT244 on FPGA outputs, UT54ACS164245SEI on pre-amp inputs to FPGA) Minor FPGA part change (RT54SX72S from RT54SX32S) Removed STE digital circuitry and interface Removed latch-up circuitry Minor part changes due to obsolescence, desire to have common parts buy and circuitry MAVEN SWEA digital board is very similar to MAVEN SWIA and STATIC: FPGA and SRAM same as SWIA, different than STATIC Housekeeping (HK MUX and ADC parts) same Fixed and Sweep DACs same minus offset DACs need for STATIC

9. Digital Board Design Command/Data Interface to PFDPU Accumulate counts from each of the 16 anodes Bin data for transfer to PFDPU Enable HVPS and MCP high voltage Control voltage sweeps for analyzer inner hemisphere and deflectors Provide programmable threshold for anode pulse amplifiers SRAM for storing lookup tables and accumulators Generate test pulses Control ADC and MUX to read instrument housekeeping monitors Note: Digital board does not control heaters (S/C) or cover actuators (S/C)

10. FPGA Block Diagram

11. SWEA and SWIA FPGA Similarities Commonalities Both require anode counting frontends Both implement Command & Telemetry Interfaces (CDI functionality for receiving commands and sending messages) Housekeeping Control and Message Format Memory Control Fixed and Sweep DAC Control Timing Backbone (reconfigured to accommodate the different accumulation intervals) Lookup table memory and control (Loader and Checksummer) High Voltage turn-on is a protected command Overcurrent Protection (shown in SWEA block diagram) to be implemented identically in both FPGAs Differences SWIA: 24 Anodes (14 WFOV and 10 NFOV) SWEA: 16 Anodes SWIA: 4 second cycle with 2304 Accumulation Intervals SWEA: 2 second cycle with 488 Accumulation Intervals SWIA Implements Products SWEA Includes Operational Heater Control

12. Digital Board Status Board Built and Loaded (MAVEN-PF-SWE-SCH-001 Rev 16) SWEA Digital

13. Digital Board Status Board Test complete per MAVEN-PF-SWE-PROC-001

14. Digital Board Status Digital Board Integrated and Tested with EM Analyzer per MAVEN-PF-SWE-PROC-002

15. Digital Board Status Fit Check with Mechanical Chassis

16. PFP Power Distribution

17. SWEA LVPS Block Diagram • Secondary Voltages • +28VA +/-10% 20mA Peak • +12VA +/-5% 8mA Peak • +5VA +/-5% 10mA Peak • -5VA +/-5% 10mA Peak • -12VA +/-5% 10mA Peak • +5VD +/-5% 40mA Peak • +3.3VD +/-3% 10mA Peak • +2.5VD +/-3% 10mA Peak

18. LVPS Status SWEA LVPS Board built, loaded and in test

19. SWEA Resources Measured: 196mW

20. Electronic Parts SWEA Active Parts List from MAVEN-PF-QA-003 Common Buy Parts • STATUS: • All parts in house or on order

21. SWEA and SWIA FPGA Similarities Immediate Schedule and Tasks Integrate and Test Digital Board/EM Analyzer with LVPS PFDPU Interface Test Further sweep Look-up Table (LUT) and memory testing Parts Stress Analysis Issues No known issues Minor changes in layout required for flight DAC polarity change Part footprint change