COMP541 More on State Machines; and Video Scanout

1. COMP541More on State Machines;and Video Scanout Montek Singh Feb 16, 2010

2. Outline • Last Friday’s lab • Tips/discussion • Look at Verilog coding practices • Avoid generating latches • Parameterized Modules • How to generate video signal

3. What did you have trouble with in lab?

4. Testing • How do you simulate/test a module that outputs a signal every millionth time?

5. Off By One? • Did you have problems if you designed a counter out of one-digit modules?

6. Good Verilog Practices • Best to use single clock for all FFs • Make all signals synchronous to one clk • no posedge button or posedge pulse • no @(signal) • not supported by current board • Avoids “weird” and frustrating problems • Multiple modules • Tested individually • Top level has input and outputs • One module per file • Just to make it easier to follow and test

7. Button Debounce • Mechanical switches can “bounce” • May get a fast series of Hs and Ls • 10s of milliseconds • How do we avoid problems?

8. Button Debounce and Synchronize • Let’s try to make it simpler this time! • Use it as input to test in an always statement that’s clocked by the master clock • State machine to detect down/up? • Wait for N clock cycles and then use it!

9. What else did you have trouble with in lab?

10. Assignment (of signals) • Continuous • Procedural • Note there are two uses for always • To generate FFs and latches (plus gates) • To generate combinational logic only • Latter does not introduce unnecessary FFs … • … if synthesizer detects all possibilities covered (i.e. no state needed) • Look at the synthesizer log

11. Procedural Assignment 1 module C2(output reg C = 0, input A, input B); always @ (A or B) case ({A, B}) 2'b11: C <= 1; default: C <= 0; endcase endmodule • Schematic next page

12. Schematic • LUT is a look-up table • Double clicking it shows

13. Procedural Assignment 2 module C1(output reg C = 0, input A, input B); always @ (A or B) begin if(A == 1 && B == 1) C <= 1; end endmodule • Synthesizer now says WARNING:Xst:737 - Found 1-bit latch for signal <C>. WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant cleaning in the block C1.

14. Schematic • LDE is latch • Small box is clock driver

15. In fact… • If I change the INIT of C like it says output reg C = 1 • Synthesizer says INFO:Xst:1304 - Contents of register <C> in unit <C1> never changes during circuit operation. The register is replaced by logic.

16. Schematic module C1(output reg C = 1, input A, input B); always @ (A or B) begin if(A == 1 && B == 1) C <= 1; end endmodule

17. Parameterized Modules 2:1 mux: module mux2 #(parameter width = 8) // name and default value (input [width-1:0] d0, d1, input s, output [width-1:0] y); assign y = s ? d1 : d0; endmodule Instance with 8-bit bus width (uses default): mux2 mux1(d0, d1, s, out); Instance with 12-bit bus width: mux2 #(12) lowmux(d0, d1, s, out);

18. VGA Monitors

19. How Do Monitors Work? • Origin is TV, so let’s look at that • LCDs work on different principle, but all signaling still derived from TV of 1940s • Relies on your brain to do two things • Integrate over space • Integrate over time

20. Many Still Images • Video (and movies) are a series of stills • If stills go fast enough your brain interprets as moving imagery • 50-60 Hz or more to not see flicker • In fact, even single “still” image displayed repeatedly over time • Phosphor persistence varies

21. Cathode Ray Tube From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

22. Deflection Coils

23. Simple Scanning TV • Electron beam scans across • Turned off when • Scanning back to the left (horizontal retrace) • Scanning to the top (vertical retrace)

24. Scanning • TVs use interlacing • Every other scan line is swept per field • Two fields per frame (30Hz) • Way to make movement less disturbing • Computers use progressive scan • Whole frame refreshed at once • 60Hz or more, 72Hz looks better

25. Color • Three colors of phosphor • Beams hit each • Black – beam off • White – all on Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

26. Aside • Frustrated with Verilog • See what to do to relieve stress http://science.howstuffworks.com/what-if-shoot-tv.htm • Educational too

27. What about LCD? • We’ll talk about how they work later • They don’t scan • However, signaling is the same! • For compatibility • Same goes for micro-mirror projectors

28. VGA Signaling • RGB and two synchronization pulses, horizontal and vertical

29. VGA Timing • You supply two pulses, hsync and vsync, that let the monitor lock onto timing • One hsync per scan line • One vsync per frame • Continuous • Don’t stop hsync Image from dell.com

30. Horizontal Timing Terms • hsync pulse • Back porch (left side of display) • Active Video • Video should be blanked (not sent) at other times • Front porch (right side) Picture not accurate for our case; just for illustration. Video and HSYNC not on same wire

31. Horizontal Timing 640 Horizontal Dots Horiz. Sync Polarity NEG Scanline time (A) 31.77 us Sync pulse length (B) 3.77 us Back porch (C) 1.89 us Active video (D) 25.17 us Front porch (E) 0.94 us This diagram shows video as a digital signal. It’s not – video is an analog level. Image from http://www.epanorama.net/documents/pc/vga_timing.html

32. Vertical Timing (note ms, not us) Vert. Sync Polarity NEG Vertical Frequency 60Hz Total frame time (O) 16.68 ms Sync length (P) 0.06 ms Back porch (Q) 1.02 ms Active video (R) 15.25 ms Front porch (S) 0.35 ms

33. Timing as Pixels • Easiest to derive all timing from single-pixel timing • How “long” is a pixel? • Active video / number of pixels • 25.17 us / 640 = 39.32ns • Conveniently close to 25 MHz – just use that • Actual VESA spec is 25.175 MHz

34. Standards • 640 x 480 (sometimes x 60Hz) is “VGA” • I will give you spec sheets in lab • You can try for 800x600 at 60 Hz (40 MHz exactly) • or 800x600 at 72 Hz (50 MHz exactly) • Note that some standards have vsync and hsync positive true, some negative true – choose correct one

35. Color Depth • Voltage of each of RGB determines color • 3-bit, 2-bit color here • All on for white

36. What To Do Friday • First finish previous lab • Make Verilog module to generate • hsync, vsync, horizontal count, vertical count, and signal to indicate active video • Use higher-level module to drive RGB using counts gated by active • Just do something simple; need to meet 25MHz constraint • Later will use memory addressed by counts to make terminal

37. What do you Need for VGA? • Think first • Need counter(s)? • Will you need a state machine? • Sketch out a design • Block diagram • Test individually in lab • Keep in Mind • Verilog has all these operators (and more; see Verilog ref.) ==, <, >, <=, >=

38. Next week’s lab: Character Terminal? • No frame buffer • Character terminal

39. Future Labs Preview • VGA timing generator • Character terminal (learn memories) • MIPS datapath • Add load/store • Add branching • Peripherals • Final project

40. VGA Links • VGA Timing • http://www.epanorama.net/documents/pc/vga_timing.html • http://appsrv.cse.cuhk.edu.hk/~ceg3480/Tutorial7/tut7.doc • Code (more complex than you want) • http://www.stanford.edu/class/ee183/index.shtml • Interesting • http://www.howstuffworks.com/tv.htm • http://computer.howstuffworks.com/monitor.htm • http://www.howstuffworks.com/lcd.htm • http://plc.cwru.edu/ • Liquid Crystals by S. Chandrasekhar, Cambridge Univ. Press

41. Next Time • Sequential Timing • Metastability • Homework due